Uk³ady steruj¹ce w zasilaczach i przetwornicach

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2 Uk³ady steruj¹ce w zasilaczach i przetwornicach Aplikacje, dane techniczne Czêœæ Gdañsk 00

3 Materia³y zebra³ i opracowa³: Opracowanie graficzne: Rysunki: Korekta: Zespó³ Redakcyjny Serwisu Elektroniki Dariusz Skulski Rafa³ Pawlak, Micha³ Kwaœniewski Edmund Tess Opracowanie zawiera aplikacje i dane techniczne uk³adów steruj¹cych stosowanych w zasilaczach i przetwornicach. Przedstawiona grupa uk³adów zosta³a tak dobrana, aby stanowiæ jak najlepsz¹ reprezentacjê dla tego typu uk³adów. Wyboru dokonano sugeruj¹c siê popularnoœci¹ uk³adów i problemami serwisowymi wystêpuj¹cymi w sprzêcie, w którym zosta³y u yte. Wydawca: Wies³aw Haligowski ul. Gen. Hallera 9/ 0 Gdañsk (0) redakcja@serwiselektroniki.com.pl Wies³aw Haligowski 00 ISBN 99 Druk i oprawa: Gdañskie Zak³ady Graficzne Spó³ka z o.o.

4 ADP I ADP00... I ADP0... II ADP0... II AH0... II AN II AN0... I AN0S... 9 II AN0SA... II AN0L... I AN0SB... I AN0L... I AN0SB... I AN I AN0... I AN0... I AN09... I AN0... I AN0... II AN0S... II AN0S... II AN0S... II AN0S... I BA90V... 9 I BA90B... I BA9... II BA9... II BA9... II BA9... II BA90A... 9 II BA90A... II BA I BA I BA II BA... II BAF... II BAN... II BA90KV... II BA90K... II BA90KV... II BA9KV... II BA9KV... 9 II BA9F... II Spis treœci BA9FS... II BA9AFV... II BA9FV... II CS9... I CS0... I CS0... I CS0... II CS0... II CS... II CS II CS... II CS... II DM... II DM... II DP0C... 9 II DPM00TA... II FA... II FA... II FA... II FA... II FA0BP(N)... II FA0AP(S)... II FA0AP(S)... II FAP(M)... II FAP(M)... II FA0CP(N)... II, II FACP(E)... 9 II FACP(N)... II FACP(E)... 9 II FACP(E)... 9 II FACP(E)(V) II FACP(N)... II FACP(E)... 0 II HAHPS/HRP... 0 II HASPS/SRP... 0 II HAHPS/HRP... 0 II HIC0... I HIS II IXBM... 0 II KAS00B... I KAS00B... I KAB... I KA... 0 I I

5 II KA... 0 I KA... 0 I KA... 0 I KAM0RQC... 0 II KAQ0RT... 0 II KAQRT... 0 II KAQRF... 0 II KAQRF... 0 II KAS0C... 0 II KAS II KAS09QT... 0 II KAS... 0 II KAS... 0 II KA00B... I KA... I KA... I L99... I L90... I L9... I L I L99/A... 0 I L99/D... I LA I LA II LA... II LF I LMA... II LMA... II LM... 0 I LM... I LM... II LM... II LM... 0 II LM... II LM... II LM... II LM... II LMA... II LT0... I LT0.... I LT0... I LT0... I LT09... II Spis treœci LT... 0 II LTC... II LTC... II LTCPLL... II LTC... II LTC... II LTC9... II M99AFP... I M99AP... I M99AFP... I M99AP... I M99FP... 0 II M99P... 0 II M09... II MA... II MA0... II MA0... I MA... I MAX0... I MAX... I MAX... I MAX... I MAX I MAX... 9 I MAX... 0 I MAX... 0 I MAX... 0 I MAX... 0 I MAX... I MAX... I MAX9... I MAX0... I MAX... I MAX00... I MAX II MAX9... II MAX9... II MAX99... II MB9... II MC0A... II MC... 0 II MC0... II MC... II

6 MC0P... I MC I MC0A... II MC... 0 II MC0... I MICC... II MICC... II MICC... II MICC... II MIC... I MIC... I MIC0... II MIC... 9 II MIC... II MIC... II MICC... II MICC... II MICC... II MICC... II MICHC... II MICHC... II MICHC... II MICHC... II MIC... II MIC0... II MIP0SY... 0 II MIP0SY... 0 II MIP0SY... 0 II MIP0SY... 0 II MIP0SY... 0 II MIP0SY... 0 II MIP0SY... 0 II ML0... I ML90... I ML9... II ML9... II ML90... II NE... I NJM I PQCG... 9 I PQCZ... 9 I PQPF... 9 I SC I Spis treœci SCX... 9 I SE... I SG... 9 I SI00... II SI0... II SI0... II SI0... II SI0S... II SI00E... II SI00S... II SI090E... II SI090S... II SI0E... II SI0S... II SI0S... II SI0L... II SI0L... II SIL... II SIL... II SI0L... II SI0L II SI0L II SI0L II SI0L II SI0L II SI0L II SI0L II SI0L II SI0L II SIL... 9 II SI9L... 9 II SI9L... 9 II SI9L... 9 II SMR II SPH I SPH II SPI00A II SPI00A II STK II STK I STK I STK... 0 I STK... 0 I III

7 IV STK... 0 I STK... I, I STK9... I STK9B... I STK I STK... 0 I STK... 0 II STKL... 0 I STK... 0 II STK... 0 I STKH I STK... 0 II STK9... I STK I, I STK... I STK... 0 II STK... I STK... I STKST... 0 II STK... 0 I STKT... I STK... I STK... I STK... I STK... I STK... I STK I STK... 9 I STK... II STK... II STK... 0 I STK90... I STK... I STK... I STK... I STK... I STKS... I STK... 0 I STK... I STK... I STK... I STK... I STK I Spis treœci STK I STK I STK0... I STK09... I STK0C... II STK I STKB... II STKC... II STKC... 0 II STK0II... I STK0II... I STK I STK0II... I, I STK... 0 I STK... I STK... I STK... I STK0... I STK0... I STK0... I STK I STK I STK I STK I STK I STK I STK I STK I STK00... I STK II STKG... II STKJ... II STKA... II STK... I STK II STR I STR00... I STR00C... I STR9... II STR00C... I STR I STR II STR II

8 STR II STR0... II STR00... II STR0... II STR... II STR... II STR I STR0... II STR I STR... II STR II STR... 9 II STR... II STR... 9 II STR II STR... I, 9 II STR... 9 II STR... 9 II STR... II STR II STR00A... I STR0B... I STR00... I STR I STRM... I STR0... I STR0... I STR0M... I STR... I STR0M... I STR... I STR... I STR I STR90... I STR00... I STR0... II STR00... II STR00... II STR00... II STR0... II STR0... II STR0... II STR II Spis treœci STR0... I STR0A... I STR... I STR9A... II STRA... I STR... II STR II STR90... II STR II STR90... II STRD I STRD0E... 0 I STRD... I STRD II STRD90E... I STRD0... II STRD09A... II STRD00X... I STRD009E... I STRD0E... I STRD0... I STRD II STRD0... I STRD I STRFLF... 0 II STRF I STRF... II STRFLF... II STRF... 9 I STRF... 9 I STRF0... II STRGT... II STRG... 0 II STRM... 9 I STRM... 9 I STRM I STRMLF... II STRMLF... 9 I STRM I STRM9LF... 0 I STRS I STRS I STRS I V

9 VI STRS I STRS0... II STRS I STRS... II STRS I STRS0... II STRS09... I STRS0... I STRS0F... I STRS... I STRS... 0 I STRSLF... I STRS0... I STRS0... I STRS0... I STRS0... I STRS09... I STRZ... I TCA0... I TCA... 0 II TDA... I TDA... I TDAG... I TDA... I TDAG... I TDA... I TDAG... I TDA... I TDA... 9 I TDA... I TDA0... I TDA... I TDA... I TDA I TDA0... I TDA00... I TDA0... I TDA I TDA I TDA I TDA... I TDAA... I TDA9GG... I Spis treœci TDA... 0 I TDA... 0 I TDA... 0 I TDA... 0 I TDA... 0 I TDA I TDA0... I TDA... I TEA09... I TEA0... II TEA0T... II TEA0... II TEA0T... I TEA0AT... II TEA0T... II TEA0T... II TEA II TEA0A... 9 II TEA09... I TEA09... I TEA I TEAA II TEA I TEA... 9 I TEA... 9 I TEA I TPS I TPS... 9 I TPS... 0 II TPS... 0 II TPS... 0 II TPS... 0 II UB... 0 II UC II UCA... 9 I UCA... 9 I VEFHA II μpc9c... 9 I

10 Od autorów Oddajemy do r¹k Czytelników drug¹ czêœæ publikacji Uk³ady steruj¹ce w zasilaczach i przetwornicach, w której kontynuujemy przegl¹d praktycznych zastosowañ uk³adów scalonych w zasilaczach i przetwornicach. Podobnie jak w pierwszej czêœci, tak i w tej, zebrane zosta³y aplikacje, a w niektórych przypadkach równie dane katalogowe uk³adów, które stosowane s¹ w zasilaczach i przetwornicach. Nie ograniczaliœmy siê tylko do przetwornic sieciowych, wystêpuj¹cych w odbiornikach telewizyjnych, monitorach, magnetowidach, czy te w sprzêcie audio. Sporo miejsca poœwiêciliœmy uk³adom pracuj¹cym w niskonapiêciowych przetwornicach DCDC, które coraz czêœciej pojawiaj¹ siê na rynku, na przyk³ad w najró niejszych ³adowarkach, a tak e sprzêcie montowanym w samochodach. Wœród uk³adów steruj¹cych prac¹ przetwornic impulsowych zasilanych napiêciem sieciowym daje siê zauwa yæ tendencjê do integracji wysokonapiêciowego tranzystora kluczuj¹cego i rozbudowanego uk³adu steruj¹cego w strukturze jednego uk³adu scalonego. Doskona³ym przyk³adem takiego rozwi¹zania s¹ uk³ady z serii MIP firmy Panasonic, w których ca³oœæ uk³ad steruj¹cy i klucz uda³o siê wcisn¹æ w trójkoñcówkow¹ obudowê TO0. Podobnie jest z uk³adami firmy Fairchild, które z regu³y upakowane s¹ w piêciokoñcówkowej obudowie TO0, np. seria KAQ, KAS Oprócz tych nowinek wœród podzespo³ów znajdziecie Pañstwo swoich starych znajomych z popularnych serii STR i STK Prezentowana ksi¹ ka nie aspiruje do rangi katalogu, mimo zamieszczenia dla czêœci uk³adów podstawowych parametrów elektrycznych. Nie jest ona zatem adresowana do projektanta, czy te konstruktora sprzêtu. Przy doborze materia³ów g³ówny nacisk po³o ono na stronê praktyczn¹, a wiêc: schemat blokowy, aplikacjê zalecan¹ przez producenta i co najwa niejsze praktyczne zastosowanie, czyli fragment schematu urz¹dzenia, w którym dany uk³ad scalony zosta³ zastosowany. Liczne opinie jakie otrzymaliœmy od Czytelników zajmuj¹cych siê serwisowaniem elektronicznego sprzêtu powszechnego u ytku po wydaniu pierwszego tomu Uk³adów steruj¹cych potwierdzi³y przyjêt¹ przez nas formu³ê tej ksi¹ ki. W sytuacji, gdy na warsztat trafia urz¹dzenie, do którego brak schematu, przyk³adowa aplikacja uk³adu pozwala na zdiagnozowanie uszkodzenia zasilacza i niejednokrotnie stanowi nieocenion¹ pomoc w naprawie. W czêœci Uk³adów steruj¹cych w zasilaczach i przetwornicach zamieœciliœmy informacje dotycz¹ce 0 uk³adów, w tomie jest ich. W celu szybkiego wyszukania ¹danego uk³adu, wzorem naszych poprzednich publikacji zamieœciliœmy spis treœci obu tomów, przy czym uk³ady wystêpuj¹ce w czêœci drugiej zosta³y wyt³uszczone. Licz¹c na przychylne przyjêcie prezentowanej publikacji podajemy nasz adres internetowy: redakcja@serwiselektroniki.com.pl, na który prosimy przesy³aæ wszelkie uwagi dotycz¹ce zarówno tomów ju wydanych, jak równie propozycji uk³adów, które powinny znaleÿæ siê w kolejnej czêœci Uk³adów steruj¹cych. Zespó³ Redakcyjny Serwisu Elektroniki

11 ADP0 sterownik zasilaczy impulsowych ADP0 V VCC SD VCCGD DLY C DLY IN OVPSET Rb DRVLSD V OUT Ra DRVL 0% Vcc V Vcc Schemat blokowy D BIAS ENABLE VCC UVLO.V DELAY.V ADP0 VCC BST DRVH SW 9 DRVL 0 P SRMON V BATT C BST Q Q

12 ADP ADP ADP0 VHYS CLSET LTO LTI LTB VID VID VID VID VID0 CLKDRV CLKFB IODRV IOFB SD PWRGD UVLO SSL SSC CORE DACOUT OUT VCC RAMP REG CS CS C C 00 Q N90 Q MJD0 C0 0 FROM CPU C 00n R.k R 0k R0 0k VRON R 0k R 0k C n C.n C 00n C p R.k C n R9 k R 0k R k C p C9 00p R k C n R.k.V R OVPSET DRVL VCC SRMON SW DRVH BST R 0k R 00k C 0p 9 0 C 0 C 00n R. C0 0 C 0 C 0 R9. M IRF M M D 0BQ00 D 0BQ00 L µ V VIN VCC ON CORE SENSE VGATE VCC CPU IO VCC CPU CLK C n R CS m R0 0 VCC CPU CORE CC, C,C C,C 0 SD IN DRVLSD DLY VCCGD P Schemat aplikacyjny

13 ADP0 podwajacz i regulator napiêcia ADP0 Schemat blokowy CP CM CP CM V OUT V IN DRV DRV DRIVE LOGIC ADP0 OVER VOLTAGE PROTECTION MHz OSC SD Schemat aplikacyjny dla nieregulowanego napiêcia wyjœciowego CP.µ C IN.0µ ADP0 V IN SD V IN V IN CM CP INPUT V IN =.V C IN.0µ CM V OUT V OUT CP 0 C 0.0µ OUTPUT V 0 9 V IN V IN CP.µ

14 ADP0 Schemat uk³adu zasilania wyœwietlacza LCD CP.µ ADP0.0µ V IN V IN V IN =.0V TO.V SD V IN CM CP.0µ V OUT V OUT.0µ k.k 0.µ.0µ V MAIN =V@ 0mA CM CP 0 9 V IN V IN 0 TL.9k CP.µ.µ.µ.0µ.0µ.0µ.0µ V GH ma ADP0.µ CP CP SD V IN V OUT NC V SNS.0µ. µ. V GL =V@ 0mA

15 AH0 sterownik zasilaczy impulsowych AH0 Zasilacz chassis P9SA firmy Samsung AC INPUT AC0V GIPIN JP* BAN GTPIN P CN0 GTPIN P F0.A AC0V BLU SW0 ESB99V MASTERSWITCH R0.M (RC) CN0.AT0L00 DCOIL P0 CR POSISTOR D00 SVCD0A ZNR C0 AC0V (MP) L0 9mH C0 AC0V (MP) L0 mh R0. 0W (RW) R0 0K /W DZ0.Vz C0 uf V C.uF V (T) 9 C 0uF 00V R0 0K /W VR0 K R.K / R0 0. W (RP) R 0 / D0 TVR0G K / R0 0 W (RS) R0 00 / R0 0K / R0 / R09 0 W (RS) Q0 CY R 0 / Q0 TCM0A C R D0 ER0 D0 ER0 IC0 AH0 A A V C0 C0 D0 ER0 C0 C0 D0 ER0 C00 AC0V L0 L0 C0 C0 SPEC mh 9mH AC0V AC0V NONSPEC JUMPER 9mH DELETE

16 AH0 C KV (RS) 0 0A Y R 0 / 0 V T0 TRANSSWITCHING A000 R0 / L0 RS0 VDD Vref C KV 9 C0 KV R0.M /W R.M /W (RC) (RC) C0 KV D0 RUAM L0 F.B L0 F.B R 0. W (RF) L0 00uH C 00uF 0V C KV D0 RUAM R 0K R0 R.K W (RS) 0K W (RS) DZ0 RKN R W (RW) C 000uF V Q0 A R W (RS) IN C09 0(P) R K /W R 90 Q0 CY MCN0 PINHEADER C 0uF 0V OUT C 0uF 0V Q0 CY DZ0.Vz C 0uF V D0 N DZ0 KAV J BV BV BV B.V BV POWER MR0 K MR00.K V POWER V HOT COLD MC0.uH 0V MQ0 A9AY MQ0 CY MQ00 CY OPTION PARTS (SIM:ADD)

17 AN900 sterownik zasilaczy impulsowych STR regulator napiêcia AN900, STR Schemat zasilacza OTVC JVC EE i ME MAIN POWER SW SW0 AC00V~0V 0/0Hz (ME) 0Hz (EE) L L L L C 0/0 C / ~ ~ F0 0,A T0 POWER TRANSF. CE000B F0 T,A C0 0,0 MM AC0V V V Q0 SA0(0) SUB POWER OUT T0 SW TRANSF. CE000B D SS ~ ~ D BB LF0 LINE FILTER TP99 V C 0,00 00V C 0 00 C0 0,0MM/AC0V V Q0, Q0 SC(Y,GR) Q0 SDB(P,Q) SUB POWER DRIVE V START D SS Q0 0V R K / Q0 9 Q0 V 0,V R,9K W,V C D 9V RDE (B) 0V R 0K 0,V Q0 FRONT IN EXT TRGG SOFT START PROTE CTOR C 0/ R9 K /W R0 K R 0K / R,9K /,9V 0,V 0,V V V V Vcc OSC V ADJ OUT OSC PULSE WIDTH MODULATOR IC0 AN900 SUB POWER R K / D0 SH TP 9 R,K / C0 0,00 MY D RD,E (B) 9 Vin Vref G G G G ERROR AMP 0,V 0,V Q0 0,V R R,K 0K / / R,K / 0,V Q0 SA0(0) MAIN START Q0 SC(Y,GR) RELAY DRIVE R 0,V Q0 D SH D SH LY0 RELAY CE000 00/W D SH I 0.Vpp (0µs/div) 9.Vpp (µs/div)

18 AN900, STR R) C 0,00 AC00V G I C 0,00 AC00V D0 C D0 D0 D0 C0 0,00 AC00V D0 D0 TVRN TH0 W POSISTOR A0 I C0 0,00 AC00V D0 GUSY C0 0/00 R0 0 W UNFR D SFJ R0 0 / R0,K / D0 SR 00 C0 00/0 T0 SW TRANSF. CJ9900C R /W D9 V9 E C 00 00V D0 RUA IC0 STR REGULATOR V V C0 0/0 R0 W/0 MR R0 0K / 0V C, 0 R0 /W 0V D0 SR00 R K / F0 TA ~ C0 00/0 D0 SFJ C09 0,0 MY 0V D09 RD0EV R0,K / TP9 K R09 K / R0 9,K / K K SX 900A POWER SUPPLY PCB ASS'Y L0 DEG. COIL Vpp (H) Vpp (H)

19 AN0S dwuwyjœciowy regulator napiêcia Schemat blokowy AN0S 9 VREF Latch IN IN FB DTC Out 0 9 VCC Latch Error amp. VREF U.V.L.O. Unlatch pro. Short pro. PWM AN0S OSC CT RT On/ Off On/Off Unlatch pro. IN Error amp. FB PWM DTC Out Opis wyprowadzeñ uk³adu AN0S Pin No. Symbol Description CT Pin for connecting the oscillation frequency setting capacitor for triangular oscillation circuit. Frequecy of triangular oscillation is set by connecting a capacitor between this terminal and RT Resistor connection pin for setting the oscillation frequency of triangular oscillation circuit. Frequecy of triangular oscillation is set by connecting resistance between the pin and On/Off "On/Off' pin for turning on/off IC. "Low" stops IC (output off) and "High" operates IC. IN Inverted input pin for channel error amplifier F/B Output pin for channel error amplifier. Gain setting or phase compensation is performed by connecting resistor or capacitor between the pin and IN. It is also connected to PWM shortcircuit protection DTC Pin for setting deadtime period of channel. The deadtime of channel is set by connecting external resistor. Soft start function can be also given by connecting capacitor in parallel with the external resistor. In addition, only channel output can be turned off by decreasing the pin voltage to below 0. V. (shortcircuit protection function stop circuit) Out Channel opencollector type output pin. Io = 00 ma maximum Grounding pin of signal system 9 Vcc Power supply voltage application pin. It detects start voltage and stop voltages 0 Out Channel opencollector type output pin. Io = 00 ma maximum DTC Pin for setting deadtime period of channel. The deadtime period of channel is set by connecting external resistor. Soft start function can be also given by connecting capacitor in parallel with the external resistor. In addition, only channel output can be turned off by decreasing the pin voltage to below 0. V. (shortcircuit protection function stop circuit)

20 0 AN0S Opis wyprowadzeñ uk³adu AN0S cd. Pin No. Symbol Description F/B Output pin for channel error amplifier. Gain setting or phase compensation is per formed by connecting resistor or capacitor between the pin and IN. It is also con nected to PWM shortcircuit protection IN Inverted input pin for channel error amplifier IN Pin for noninverted input of channel error amplifier Latch Pin for connecting the time constant setting capacitor for timer latch type shortcircuit protection circuit. The time constant for shortcircuit protection is set by connecting a capacitor between this terminal and V REF typical or more is applied, the overcurrent protection operates to reduce VREF and Internal reference voltage output pin (. V(allowance: ±%)). If a load of 0 ma switching operation stops Schemat aplikacyjny V IN =V 00.V 0.0µ 00.V 0k 0.µ k VCC =V 0µ CT VREF VREF U.V.L.O. 0p OSC RT Latch 0k Latch On/Off IN On/ Off Short pro. Unlatch pro. IN IN Unlatch pro. R FB FB Error amp. Error amp. 0k 0.0µ 0.µ DTC DTC PWM PWM Out Out k VCC AN0S VCC =V 00 V k 0.V k

21 AN0S Schemat aplikacyjny k V SBD V k k 0.0µ k 0k 0.µ k VCC CT VREF V REF U.V.L.O. 0p OSC RT Latch 0k Latch On/Off IN Short pro. Unlatch pro. On/ Off IN IN Unlatch pro. Error amp. FB FB Error amp. 0k 0.0µ V 0.µ DTC DTC PWM PWM k Out Out 0 9 SBD VCC AN0S k V k V SBD V f = 00kHz Duty = % k k To pin

22 AN0SA AN0SA dwuwyjœciowy regulator napiêcia Schemat blokowy Vcc VREF OSC DT 9 On/ off FB IN IN On/off control Error amp. Reference.9V voltage source V REF Triangular wave oscillation Unlatch U.V.L.O. H L 0.V VREF 0.9V PWM Out FB 0.9V Error amp. 0.V IN.9V S.C.P. comp. AN0SA 0.9V VREF R S Latch Unlatch Q 0.9V VREF PWM Vcc RB 0 Out S.C.P. DT Opis wyprowadzeñ uk³adu AN0SA Pin No. Symbol Description Pin No. Symbol Description Pin for oscillation timing Grounding pin OSC resistor and capacitor connection 9 Vcc Power supply voltage application pin Pin for connecting the time 0 Out Out block pushpull type output pin S.C.P. constant setting capacitor for shortcircuit protection RB IN IN FB DT Out Out block output source current setting resistor connection pin Error amplifier block noninverting input pin DT PWM block deadtime setting pin Error amplifier block inverting input pin Output pin of error amplifier block PWM block deadtime setting pin Out block opencollector type FB Output pin of error amplifier block IN Error amplifier block inverting input pin Off On/off control pin output pin V REF Reference voltage output pin

23 VREF Off IN FB DT AN0SA Schemat aplikacyjny dla napiêcia wejœciowego V i napiêæ wyjœciowych V/V k 0.0μ to 0.μ 0.μ SW 0.0μ RB AN0SA Input V k 0.μ k Out 0 0μ VCC 9 00μH MAX0 (MA0*) 0μ SD00 Output V, 0mA 0k k OSC S.C.P. IN IN FB DT 0p k 0.0μ k 0.0μ k Out 00 0 Output V, 0mA k k k k k 0.μ 00μH MAX0 (MA0*) 0μ Schemat aplikacyjny dla napiêcia wejœciowego..v i napiêæ wyjœciowych V/V Input k 0.0μ to 0.μ 0.μ H L 0.0μ k VREF Off IN FB DT k RB 0.μ k Out 0 0μ VCC 9 0μH 00μ Output V 0k k AN0SA OSC S.C.P. IN IN FB DT 0p k 0.0μ k 0.0μ 0k k k Out μ 0μH 00μ k Output V 9k 9k

24 AN0SA Remote on/off control pin 0V, V, V stop with highlevel input..9v.9v 0.μ 0.μ VREF OSC k VREF OSC Off S.C.P. Off S.C.P. IN IN IN IN FB IN FB FB DT FB 0p k k 0.μ 0.μ k Schemat wspó³pracy uk³adu AN0SA z uk³adem AN0SA Input voltage range:.v to.v Oscillation frequency: 0kHz DT DT Input.V to.v RB DT RB RB 0.μ 0 Out Out k k k 0.μ 0.μ k 0.μ k k 0.μ k k 0k 0k k 0.μ 0 AN0SA 0k 0k Out Out 0 0 VCC VCC 9 AN0SA 0 9 μh 0μH 0μH 00 SD0 SB0 μh 0μ 0μ 0μ 0μ MAQ (MA*) MAQ (MA*) k9 k SD00 MAQ (MA*) SD00 MAQ (MA*) V (STBY) 00mA (max.) 9k k k 0V 0mA (max.) V 0mA (max.) k V ma (max.)

25 AN0, AN0S AN0, AN0S sterowniki zasilaczy impulsowych Schemat blokowy VCC OVP OVP R S (SD latch) Q INIT Start Stop V REF V RSTB IFB TR k k V I/V conv. Highside clamp.v VFB Current reviser(itr) Lowside clamp 0.V R Q S (TR latch) Current reviser(ifb).0v TON TOFF Q Q Q CF latch Q S R Q Q R AN0 AN0S In In Out drive 0.V Out CLM CF Uk³ady AN0 i AN0S ró ni¹ siê obudowami: AN0 pin DIP AN0S pin SOP

26 AN0, AN0S Opis wyprowadzeñ uk³adów AN0 i AN0S Pin No. Symbol Description TR Transformer reset. When a transformer reset is detected, i.e., a low level is input to this pin, the IC output goes high. However, the transformer reset signal is ignored during the minimum offperiod determined by the CF pin. The maximum onperiod is also corrected according to the current flowing out of this pin. RSTB Adjusts the lightload detection level that determines the when the IC switches from RCC to discontinuous operation. When the voltage (V FB ) which is IV conversion of current feedback signal from IFB pin goes up higher than this pin, minimum offperiod current at CF pin decreases, and operating frequency decreases. The detection level can be adjusted arbitrarily using an external pulldown resistor. CF Connection for the capacitor that determines the on and off periods for the IC output (Out). IFB Input for the current feedback signal from the power supply output photocoupler CLM Input of the pulsebypulse overcurrent protection circuit. Normally, it will be necessary to add an external filter for this input. Ground. V OUT Output to drive a power MOSFET directly. Vcc Power supply. This pin watches Vcc and has operating threshold voltages for the start, stop, OVP and OVP reset levels. Schemat aplikacyjny E IN V OUT CC PC ANMS RSTB IFB AN0 AN0S Out PC TR CLM CF EIN

27 AN0, AN0S.0V/0.A R0 0 R 00 R k R 0 C μ C 000μ C μ PC Q ANM/T R k D C 000μ MAF0 (MA0) MAD9 (MA09) D D9 MAD0 (MAD0) V/0mA FBI R Q SK C C 00p R 0 R 0. R PC R k C9 0.0μ R k R k C 0μ ~ ~ ~ C L C C C C L C0 00μ S C 000p MAC00 (MA00) MAC00 (MA00) 0.0μ S k AN0, AN0S CLM FB CF Out RSTB Vcc TR R R R0 k D MAC (MA) D MAC (MA) D MAC (MA) R 0 V/0.A Rozszerzony schemat aplikacyjny

28 AN0S AN0S uk³ad sterowania podœwietleniem w wyœwietlaczach LCD Schemat blokowy VREF DTC CT RT V CC Off VREF.V On/off activehigh Constant current source PWM comp OSC Bootstrap CB Out S.C.P. R Q U.V.L.O. S Q R Latch Q S AN0S S.C.P. comp. Error amp. Error amp. FB IN IN 9 FB IN 0 IN Opis wyprowadzeñ uk³adu AN0S Pin No. Symbol Description Pin No. Symbol Description V REF Reference voltage output pin IN Error amplifier inverted input pin RT Pin for connecting oscillator FB Error amplifier output pin timing resistor 9 FB Error amplifier output pin CT 0 IN Error amplifier inverted input pin Pin for connecting oscillator Error amplifier noninverted input timing capacitor IN pin DTC Deadtime control pin Grounding pin Pin for connecting the time Out Output pin constant S.C.P. CB Bootstrap output circuit setting capacitor for shortcircuit protection Vcc Power supply voltage application pin IN Error amplifier noninverted input pin Off On/off control pin

29 AN0S 9 Schemat aplikacyjny podœwietlenia wyœwietlacza LCD In k 0.µ SBD V 0.V k 9k 0.0µ 0p k VREF DTC CT RT VCC Off V.V REF On/off activehigh Constant current source PWM comp OSC Bootstrap CB Out R S S.C.P. R S U.V.L.O. Latch AN0S Q Q Q S.C.P. comp. 0p.V Error amp. Error amp. 9 0 FB IN IN FB IN IN V k k SBD L A M P

30 0 AN0S PWM comp OSC Off S.C.P. Schemat aplikacyjny konwertera DCDC In V VREF DTC CT RT VCC V.V REF On/off activehigh Constant current source Bootstrap R S R S U.V.L.O. Latch AN0S Q Q Q S.C.P. comp..v Error amp. Error amp. 9 0 CB Out FB IN IN FB IN IN V SBD Out

31 AN0S AN0S sterownik niskonapiêciowych zasilaczy impulsowych Schemat blokowy RESET Vcc EMP VSEN START CT VREF 0.V VREF 0.V 0.V.V.V.V Starter SW Early Value Set..0.V Starter Triangular Wave 9 CLK PVcc 0.V.V.0V Power OFF POWER 0K 0.V Switching Circuit 0.9V K AN0S RESET EMP IN FB SPRO DED OUT Przyk³adowy schemat aplikacyjny.v ±0.V.V.V VREF.V.0.V.V Starter SW Early Value Set. 0.V.V.0V START 0pF k 0 Starter 0.V 0.V Triangular Wave Power OFF 9 CLK 0K 0.9V 0.V K Switching Circuit AN0S µf 0.0µF k 0.0µF Start oscylatora: n. pod³¹czona do strony wtórnej, n.0 pod³¹czona do masy (n.0 jest niepod³¹czona podczas pracy uk³adu) 0.0µF 00R

32 AN0S Opis wyprowadzeñ uk³adu AN0S Nr nó ki Symbol Funkcja IN Wejœcie wzmacniacza b³êdu FB Wyjœcie wzmacniacza b³êdu SPRO Wejœcie uk³adu zabezpieczaj¹cego w przypadku zwarcia DED Wejœcie sterowania czasem zw³oki. Maksymalne obci¹ enie jest ustawione na %. Obci¹ alnoœæ mo e byæ zmieniana przez do³¹czenie zewnêtrznego rezystora pomiêdzy nó kê i OUT Wyjœcie do sterowania tranzystorem wykonawczym (kluczem). Maksymalny pr¹d wyjœciowy wynosi 0mA Masa CT Kondensator przebiegu pi³okszta³tnego PV CC Wejœcie napiêcia sta³ego, które powinno wynosiæ.v lub wiêcej 9 CLK Wejœcie zegara do synchronizacji przebiegu pi³okszta³tnego 0 START Wejœcie uk³adu inicjuj¹cego pracê uk³adu POWER W³¹czanie/wy³¹czanie impulsów wyjœciowych. Wyjœcie jest wy³¹czone przy stanie niskim (L) na n. V REF Napiêcie odniesienia EMP Wyjœcie uk³adu wykrywaj¹cego malenie napiêcia VSEN Wejœcie uk³adu detekcji zmniejszania napiêcia Reset Wyjœcie resetu V CC Napiêcie zasilania, którego wartoœæ powinna byæ wiêksza od.v Podstawowe parametry: napiêcie zasilania V CC. V PV CC. V pobór pr¹du IPV CC.mA (V cc =.V, PV cc = V) napiêcie wyjœciowe V O.V czêstotliwoœæ oscylatora f OSC 0 0kHz (C T = 0pF, R REF = k) AN0S obudowa: SOP

33 BA9 BA9 uk³ad systemu zasilania poszczególnych bloków zestawu audio Vcc Vcc Vcc Vcc Vcc Vcc Schemat blokowy BA9 REGULATOR 9 0 AUDIO 9V C PRE RADIO V COM V CD V CD V MODE SW Vcc REF STB MOTOR.V Opis wyprowadzeñ uk³adu BA9 Pin No. Pin name Function AUDIO 9V AUDIO 9V output C Capacitor for regulating AUDIO 9V PRE AUDIO system RADIO V RADIO V output pin; output when MODE SW is.v (typical) COM V Microcontroller V output CD V CD V output pin; output when MODE SW is.v (typical) CD V CD V output pin; output when MODE SW is.v (typical) MODE SW Pin to select CD V, CD V, or RADIO V output 9 Vcc Power supply 0 REF STB Reference voltage V output pin; also a standby SW MOTOR.V MOTOR.V output Large current, connected to the IC substrate

34 BA9 BA9 uk³ad systemu zasilania poszczególnych bloków zestawu audio Vcc Vcc Vcc Vcc Vcc Vcc Schemat blokowy BA9 REGULATOR 9 0 AUDIO.V C PRE RADIO V COM V CD V CD.V MODE SW Vcc REF STB MOTOR 9V Opis wyprowadzeñ uk³adu BA9 Pin No. Pin name Function AUDIO.V AUDIO.V output C Pin to connect a capacitor that regulates AUDIO.V PRE AUDIO system RADIO V RADIO V output ; output when MODE SW is.v (typical) COM V Microcontroller V output CD V CD V output ; output when MODE SW is.v (typical) CD.V CD.V output MODE SW Pin to select CD V, CD.V, or RADIO V 9 Vcc Power supply voltage. 0 REF STB Reference voltage V output ; also a standby SW MOTOR 9V MOTOR 9V output Large current, connected to the IC substrate

35 BA9 REGULATOR Schemat aplikacyjny BA9 Vcc Vcc Vcc Vcc Vcc Vcc CD 9 0 MOTOR REF STB Vcc MODE SW CD Dr CD CONT COM PRE C RADIO AUDIO 0µ REF MOTOR DRIVER Vcc 0µ 0µ 00µ 0µ M 0µ M M CONT V Line System control Remote control V BACK UP LINE IN POWER AMP GEQ LINE AMP R/P AMP TUNER

36 BA9 BA9 uk³ad systemu zasilania poszczególnych bloków zestawu audio Vcc Vcc Vcc Vcc Vcc Vcc Schemat blokowy BA9 REGULATOR 9 0 AUDIO 9V C PRE RADIO V COM V CD V CD.V MODE SW Vcc REF STB MOTOR 9.V Opis wyprowadzeñ uk³adu BA9 Pin No. Pin name Function AUDIO 9V AUDIO 9V output C Capacitor pin for regulating AUDIO 9V PRE AUDIO system RADIO V RADIO V output ; output when MODE SW is.v (typ) COM V Microcontroller V output CD V CD V output ; output when MODE SW is.v (typ) CD.V CD.V output ; output when MODE SW is.v (typ) MODE SW Pin to select CD V, CD.V, or RADIO V 9 Vcc Power supply 0 REF STB Reference voltage V output ; also a standby SW MOTOR 9.V MOTOR 9.V output Large current, connected to the IC substrate

37 BA9 BA9 uk³ad systemu zasilania poszczególnych bloków zestawu audio Schemat blokowy BA9 Vref Vob Vo Vo k STB k Vcc NPN Vo Vo C PRE Vo Przebiegi czasowe Vcc STANDBY voltage Vcc B OUT V OUT V OUT.V OUT 9V Timing chart

38 BA9 Schemat aplikacyjny LINE IN R/P AMP LINE AMP GEQ POWER 0µ 00µ 0µ C CD V AUDIO 9V Vcc B MOTOR V BA9 0µ OUT.V PRE M CD MOTOR DRIVE 0µ System control CONT M M Opis wyprowadzeñ uk³adu BA9 Pin No. Pin name Function Vcc B output 0mA output current interlocked with Vcc Vcc DC supply input External transistor collector Output pin for external transistors External transistor base Base pin for external transistors V output 0mA power supply output current. V output 0mA power supply output current 9 V output 00mA power supply output current C Capacitor pin for improving the 9V output ripple rejection 9 N.C. 0 STAND BY Pin for ON/OFF control of each output PRE Small current Large current

39 BA90A 9 BA90A uk³ad systemu zasilania poszczególnych bloków zestawu audio Schemat blokowy V CC Vref OUT 9V 00mA 0 C OUT V A ST 0 BA90A.V V MODE 9 0 C OUT V 00mA 0 OUT V 0mA 0 Opis wyprowadzeñ uk³adu BA90A Pin No. Pin name Function C Capacitor pin for improving the 9V output ripple rejection OUT9V 9V output OUTV V output (current capacity = A) C Capacitor pin for improving the V (A) output ripple rejection N. C. Not used V CC V CC input OUTV V output (current capacity = 00mA) OUTV V output 9 MODE Switch pin for V outputs 0 ST Standby switch N. C. Not used

40 0 BA90A Blokowy schemat aplikacyjny LINE IN R/P AMP LINE AMP GEQ POWER CD MOTOR DRIVE M M System control OUTV OUT9V C OUTV (00mA) MODE BA90A V CC ST OUTV (A) C 0 MOTOR DRIVE M 00 M Podstawowe parametry maksymalne napiêcie zasilania V CC V maksymalna moc rozproszenia 000mW (P = P {(V CC V) I OUT } P {(V CC V) I OUT } P {(V CC 9V) I OUT } P {V CC I zasilania })

41 BA90A BA90A uk³ad systemu zasilania poszczególnych bloków zestawu audio Schemat blokowy Vcc Vref MAIN SIGNAL V 0.A 0µ ST 0 µ MOTOR.V 0µ MODE SELECT 9 CDP 0V 0.A 0µ µ µ COM.V 00mA BA90A 0µ Przebiegi czasowe The MAIN, MOTOR, and µcom outputs rise when ST is.v (Typ.). The CDP output rises when MODE is.v (Typ.) and ST is.v (Typ.). Vcc ST MODE MAIN SIGNAL MOTOR CDP µ COM Timing chart

42 BA90A Schemat aplikacyjny LINE IN R/P AMP LINE AMP GEQ POWER 0µ µ 0µ µcom MAIN C Vcc µ 0µ CDP C ST BA90A MODE MOTOR B MOTOR C 0µ 00µ CD MOTOR DRIVE System control MOTOR DRIVE M M M M Opis wyprowadzeñ uk³adu BA90A Pin No. Pin name Function MOTORB Pin for external transistor base MOTORC Pin for external transistor collector COM.V output C Capacitor pin for improving the 0V output ripple rejection CDP 0V output Vcc Vcc input C Capacitor pin for improving the V output ripple rejection MAIN V output 9 MODE Mode switching 0 ST Standby switching N. C. Not used

43 BA900 BA900 uk³ad systemu zasilania poszczególnych bloków zestawu audio Schemat blokowy REGULATOR BA900 OVERVOLTAGE PROTECTION 9 0 FM.0V RADIO.0V AMP Vcc ANT COM.0V MODE MODE STB VDD.V VAR 0.0V

44 BA900 Schemat aplikacyjny AUTO ANT M IGN ACC KEY BATT BA900 B/T MAIN AMP RADIO CS FM RADIO COM ANT Vcc AMP VDD STB 0µ 0µ 0µ 0µ 0µ MODE IGN VDD MODE MODE VAR 0µ CPU MODE STB

45 BA900 Opis wyprowadzeñ uk³adu BA900 Pin No. Pin name Function VAR output 0.0V power supply for variable capacitor; maximum output is.ma. MODE SW RADIO, ANT, and VAR outputs are turned ON when this pin is V. MODE SW FM output is turned ON when this pin is V. STAND BY COM and AMP outputs are turned on when this pin is V; only V DD is output in standby mode (0V). V DD output. V Power supply for a microcontroller; maximum output is 00mA; output is always available if BACKUP power supply is connected. AMP output Power supply to drive a remote amplifier; a voltage of about V (typical) lower than the Vcc pin voltage is provided with a maximum output of 00mA. Vcc Connected to car BACKUP and ACC power supplies. ANT output Power supply to drive an antenna; a voltage of about V (typical) lower than the Vcc pin voltage is provided with a maximum output of 00mA. 9 COM output.0v power supply with a maximum output of 0mA; this can be used as system common power supply (such as tone, volume, and balance control) as well as power supply for cassette player equalizers and electronic tuning variable capacitors. 0 RADIO output.0v main power supply with a maximum output of 0mA for radio FM output.0v power supply with a maximum output of 0mA for FM receiver Connected to the IC substrate. Przebiegi czasowe BACK UP (Vcc) VDD output STAND BY COM output AMP output MODE SW MODE SW FM output RADIO output ANT output VAR output Input/output timing chart

46 BA BA regulator napiêcia Fragment zasilacza magnetowidu VSEOG MK II firmy Akai D D TR V REG V VOLTAGE MONITER V REG CONTROL V UNR V TO IDL9V, AL9V TR V REG V V TO DIGITAL CIRCUIT TR VOLTAGE DETECT & PROTCTION D HZ D V REG V VOLTAGE MONITER V REG CONTROL TR V IDLV REG TR TR PCB IDLV MOTOR V D to D 0V REG TR 0V VOLTAGE MONITER V REG CONTROL AC.V D to D C POWER SAVE 0 VCC V REG TRIANGLE OSC PRE (A) DRIVER.V PRE (B) DRIVER.V PRE (C) DRIVER PRE (D) DRIVER 9 V REG CONTROL VOLT MONITER V REG CONTROL VOLT MONITER NC SW DRIVE TR AMP D C C0 0V TO TUNER VT CIRCUIT.V 0V VOLTAGE MONITER D IC BA SWITCHING REGULATOR AC.V D C C9 V TO OPERATION FLD DRIVE AC.V TO FLD

47 BAN, BAF BAN, BAF sterownik przetwornicy Schemat blokowy BAN BAF DRIVE FB BLOCKING OSCILLATOR NC NC NC BLOCKING OSCILLATOR NC Vin FB DRIVE NC Vin Schemat aplikacyjny Vin L.mH Rc k C µ C.µ C.µ 00k RL DRIVE FB NC NC NC NC Vin BAF Opis wyprowadzeñ uk³adów BAN, BAF Nr nó ki BAN BAF Sprzê enie zwrotne Wyjœcie oscylatora Zasilanie Masa,,, Niepod³¹czone Funkcja

48 BA90KV BA90KV czterowyjœciowy sterownik zasilaczy impulsowych Schemat blokowy STB DT FB INV NON NON INV FB DT VE OUT OY 0 9 VDD VREF SCP SYNC CTLS RTC RT CT ERR ERR VREF AMP AMP REFERENCE PWM REGULATOR COMP SCP COMP 9 VREF VREF 0 / VREF PWM U.V.L.O. COMP TIMER SLATCH R 0 Q / DIVIDER 9 TRIANGLE OSCILATOR BA90KV VREF VREF PWM COMP OX VCC OX OY OUT VE VE OUT OY RT CT CTLB PWM COMP TRIANGLE OSCILATOR / DIVIDER ERR ERR AMP AMP OX VCC OX 9 0 DT FB INV NON STB NON INV FB DT VE OUT OY

49 BA90KV 9 Opis wyprowadzeñ uk³adu BA90KV Nr nó ki, 9,, (odpowiednio dla ka dego kana³u),, 9, (odpowiednio dla ka dego kana³u),, 0, (odpowiednio dla ka dego kana³u),,, (odpowiednio dla ka dego kana³u) Funkcja Ustawienie czasu resetu. Okres resetu ustawiany jest przez dzielenie, na zewnêtrznym rezystorze, napiêcia VREF. agodny start realizuje siê przez do³¹czenie do tych nó ek i VREF kondensatora Wyjœcie wzmacniacza b³êdu. Wzmocnienie i faza regulowane s¹ przez rezystor i kondensator do³¹czone do tej nó ki i INV Wejœcie odwracaj¹ce wzmacniacza b³êdu Wejœcie nieodwracaj¹ce wzmacniacza b³êdu ON/OFF dla kana³u. Kana³ pracuje, gdy na nó ce tej jest stan wysoki 0,, 9, (odpowiednio dla ka dego kana³u),, 0, (odpowiednio dla ka dego kana³u),,,,,,, (odpowiednio dla ka dego kana³u) Ustawianie wartoœci pr¹du wyjœciowego. Ustawianie to odbywa siê przez do³¹czenie do tej nó ki masê rezystora o odpowiedniej wartoœci Wyjœcie Ustawianie wy³¹czenia pr¹du wyjœciowego, odbywa siê to przez do³¹czenie miêdzy OX i OY kondensatora, Wyjœcie napiêcia zasilania ON/OFF dla wszystkich kana³ów. Je eli na nó ce tej jest stan wysoki nastêpuje zatrzymanie pracy wszystkich kana³ów Zasilanie Wyjœcie napiêcia odniesienia 9 Masa 0 Kondensator sta³ej czasowej uk³adu zabezpieczenia przed zwarciem. Kondensator ten do³¹czony jest miêdzy t¹ nó k¹ a mas¹ Wejœcie zewnêtrznych, trójk¹tnych impulsów synchronizacji Wejœcie ON/OFF dla zewnêtrznej synchronizacji impulsami trójk¹tnymi. Obwód zewnêtrznej synchronizacji pracuje, gdy na tej nó ce jest stan wysoki Kondensator stabilizuj¹cy czêstotliwoœæ przebiegu pi³okszta³tnego Rezystor ustalaj¹cy czêstotliwoœæ przebiegu pi³okszta³tnego Kondensator ustalaj¹cy czêstotliwoœæ przebiegu pi³okszta³tnego Rezystor ustalaj¹cy czêstotliwoœæ przebiegu pi³okszta³tnego dla silników Kondensator ustalaj¹cy czêstotliwoœæ przebiegu pi³okszta³tnego dla silników ON/OFF dla przebiegu pi³okszta³tnego dla silników. Generator tego przebiegu pracuje, gdy na nó ce tej jest stan wysoki Podstawowe parametry: napiêcie zasilania. V maksymalna, dopuszczalna moc 00mW

50 0 BA90KV Fragment schematu DVD L0 firmy Panasonic J00 VJJ00 DC IN (NC) 0A B A OUT OPR L0 VLQ09 C0 000p E SWM,V PSW R00 00k TC00 NP C0 0, R00 0k C00 R00 0μ k V L0 VLQ0MRT L00 VLQ0MRT C00, Q00 SB90X PSW R00 k C00 μ V R0 0k R0 9k C00 μ V C0 C0, R00 k C00 μ V R00 k R009 0 R00 0 R00 0 C00 C00 00p 0,0 A OPR OPRONH QR00 UN HOLD QR00 UN VDD VREF STB DT FB IN IN IN D00 MA0LTX C0 0, 9 C0 QR00 UN 0 SCP C0 0μ V SYNC CTLS C0 0,0 RTC R0 k9 C0 0p RT CT R0 k RT C09 0p CT 0C A OUT A ORP,V PONH Q00 SB90X R09 k R0 0k QR00 UN R00 k R0 0 CTLB R0 0 DTC FB IN IN STB IN C00 00p C0 0,0 A ORP LCDONH R0 0 C0 0,0 C0 00 ONLY P0 K00 K00

51 BA90KV R00 0 C009 00p C00 0, DTC VE OUT DY FB IN IN ONLY L0 00 IC00 BA90KV FB DT VE OUT DY OX VCC OX OY OUT VE VE OUT OY OX VCC OX IN IN R0 C00 0, C0 0p C0 μ 0V R0 k R0 k C0 p C0 p C09 0p R0 R0 9 C00 00p C0 p C0 p R0 C0 0p Q00 SB9 SW R0 /W 00 C0 0p CP00 C0 0, C0 μ C00 0p L00 VLQM0T R0 C0 μ C0 μ C0 μ C0 μ D00 MATX D00 SB00CPTB T00 VLT09 R0 D00 MATX R0 R0 k L009 VLQ09K0 L0 VLQ09K0 L00 VLQ09K00 R0 0k C0 μ D00 SB00PTD L00 VLQM0T C0 μ C0 μ Q00 SA9STD REG R0 C0 0,0 C0 0p R0 k R0 0 R09 k L00 VLQMRT C09 μ C0 0, R0 0 R0 k R0 0 C0 00p L00 VLQMRT L00 VLQMRT C0 0,0 R00 0 R0 k L00 VLQMRT C0 0p R0 0 R09 k L00 VLQM0T Q00 FR0TL Q009 FP0TL REG REG R0 k

52 BA90K BA90K trójwyjœciowy sterownik zasilaczy impulsowych Schemat blokowy SYNC STB NON INV FB DT SCP BUF 0 9 V DD ERR AMP VE V REF REFERENCE REGULATOR V REF PWM COMP OUT CT Vcc RT TRIANGLE OSCILLA TOR SCP COMP TIMER SLATCH R Q V REF U.V.L.O. STB NON 9 0 ERR AMP BA90K PWM COMP VE OUT V REF INV 0 DT PWM COMP FB ERR AMP V REF 9 OUT NON INV FB OY OX OY OX VE Opis wyprowadzeñ uk³adu BA90K Pin No. Pin name Function NON Channel error amplifier noninverted input INV Channel error amplifier inverted input FB OY OX Channel error amplifier output pin; gain setting and phase compensation are controlled by connecting a resistor and capacitor between this pin and the INV Channel output transistor off current setting pin; output transistor off current is set by connecting a capacitor between the OX and OY

53 BA90K Opis wyprowadzeñ uk³adu BA90K cd. Pin No. Pin name Function OY Channel output transistor off current setting pin; output transistor off current is set OX by connecting a resistor and capacitor VE Channel output current setting pin; output current of OUT is set by connecting a resistor between this pin and 9 OUT Channel output 0 DT Channel rest period setting pin; the rest period of Channel is set by dividing the VREF voltage with external resistors; a soft start is possible by connecting a capacitor between this pin and VREF OUT Channel output VE Channel output current setting pin; output current of OUT is set by connecting a resistor between this pin and STB ON/OFF pin for all Channels; stops the reference voltage and all Channel operations when the pin is HIGH level V CC Output power supply OUT Channel output VE Channel output current setting pin; output current of OUT is set by connecting a resistor between this pin and BUF Triangular wave external output pin, which makes triangular waves available to outside the IC SCP Pin for connecting a timeconstant setting capacitor in the shortcircuit protection circuit; time constant for the timerlatched, shortcircuit protection circuit is set by connecting a capacitor between this pin and 9 DT Channel rest period setting pin; the rest period of Channel is set by dividing the VREF pin voltage with external resistors; a soft start is possible by connecting a capacitor between this pin and VREF 0 FB Channel error amplifier output pin; gain setting and phase compensation are controlled by connecting a resistor and capacitor between this pin and the INV INV Channel error amplifier inverted input NON Channel error amplifier noninverted input STB Channel ON / OFF pin; Channel operates when the pin is HIGH level, and ceases operation at LOW level; this pin is valid when CTL is LOW level SYNC Pin for triangular wave external synchronization input; capacitorcoupled AC wave is input, and the triangular wave is synchronized with the input frequency; the pin is used in the case of selfoscillation V DD Power supply VREF Reference voltage output ;. V (typical) CT Pin for connecting a frequency setting capacitor in the triangular wave oscillation circuit; triangular wave oscillation frequency is set by connecting a capacitor between this pin and RT Pin for connecting a frequency setting resistor in the triangular wave oscillation circuit; triangular wave oscillation frequency is set by connecting a resistor between this pin and 9 Ground 0 NON Channel error amplifier noninverted input INV Channel error amplifier inverted input FB Channel error amplifier output pin; gain setting and phase compensation are controlled by connecting a resistor and capacitor between this pin and the INV

54 BA90KV BA90KV czterowyjœciowy sterownik zasilaczy impulsowych Schemat blokowy STB DT FB INV NON NON INV FB DT VE OUT OY 0 9 V DD V REF SCP SYNC 9 0 REFERENCE REGULATOR SCP COMP Vref TIMER LATCH S Q R ERR AMP ERR AMP U.V.L.O. V REF V REF PWM COMP PWM COMP 0 OX V CC OX OY OUT CTLS / DIVIDER V REF 9 VE RTC VE PWM COMP RT CT TRIANGLE OSCILATOR V REF OUT OY PRO PRO STB ERR AMP BA90KV ERR AMP PWM COMP OX V CC OX 9 0 DT FB INV NON STB NON INV FB DT VE OUT OY

55 BA90KV Opis wyprowadzeñ uk³adu BA90KV Pin No. Pin name Functions, 9,, DT Rest period setting pin; the rest period is set by dividing the VREF pin voltage with external resistors; a soft start is possible by connecting a capacitor between this pin and VREF.,, 9, FB Error amplifier output pin; gain setting and phase compensation are controlled by connecting a resistor and capacitor between this pin and the INV.,, 0, INV Error amplifier inverted input,,, NON Error amplifier noninverted input STB Channel ON/OFF pin; Channel operates when the pin is HIGH level; this pin is valid when STB is LOW level. 0,, 9, VE Output current setting pin; output current is set by connecting a resistor between this pin and.,, 0, OUT Output,,,,,,, OX, OY Output off current setting pin; output off current is set by connecting a capacitor between the OX and OY., V CC Output power supply STB ON/OFF pin for all Channels; stops the reference voltage and all Channel operations when the pin is HIGH level. V DD Power supply VREF Reference voltage output 9 Ground 0 SCP Pin for connecting a timeconstant setting capacitor in the shortcircuit protection circuit; time constant for the timerlatched, shortcircuit protection circuit is set by connecting a capacitor between this pin and. SYNC Pin for triangular wave external synchronization input; capacitorcoupled AC wave is input, and the triangular wave is synchronized with the / subharmonic oscillation of the input. CTLS ON/OFF pin for triangular wave external synchronization input; external synchronization circuit operates when the pin is HIGH level. RTC Pin for connecting a capacitor to stabilize the triangular wave oscillator constant current; noise of the constant current is reduced by connecting a capacitor between this pin and. RT Pin for connecting a resistor to set the triangular wave oscillator frequency; oscillation frequency is set by connecting a resistor between this pin and. CT Pin for connecting a capacitor to set the triangular wave oscillator frequency; oscillation frequency is set by connecting a capacitor between this pin and. PRO Pin to set shortcircuit protection in an arbitrary way; connected to VREF when not used. PRO Pin to set shortcircuit protection in an arbitrary way; connected to VREF when not used. STB Channel ON/OFF; Channel operates when this pin is HIGH level; this pin is valid when STB is LOW level.

56 BA9KV BA9KV szeœciowyjœciowy sterownik zasilaczy impulsowych Opis wyprowadzeñ uk³adu BA9KV Pin No. Pin name Function,,, 9,, CAPL,,,,, L connection for off transistor current setting capacitor,,,,, 9 CAPH,,,,, H connection for off transistor currentsetting capacitor,,,,, BIAS,,,,, Output current setting,, 0,,, OUT,,,,, Power transistor base connection 9,,,,, SCP,,,,, Output voltage monitor for ch to ch protection,, 9,,, 0 INV,,,,, Inverting input for error amplifier,, 0,,, 9 FB,,,,, Error amplifier output COMP Timer latch external trigger input RT Connection for resistor for triangularwave timing CT Connection for capacitor for triangularwave timing SCP Connection for capacitor for setting timing latch delay DUTY MOSFET duty control Ground SOFT Connection for capacitor for setting soft start Vref Reference voltage output Vcc Power supply input 9 STB Channel on / off switch 0 STB All Channel on / off switches, DTC, Dead time control, 0 GATE, MOSFET gate connection Vcc Power supply input for Channels and output stages Vcc Power supply input for Channels and output stages Vcc Power supply input for Channels and output stages Ground connection for Channels,, and output stages Ground connection for Channels,, and output stages 0, NON, Noninverting input for error amplifier Podstawowe parametry napiêcie zasilania..v maksymalny pr¹d wyjœciowy 00mA czêstotliwoœæ wewnêtrznego oscylatora 0 00kHz rezystor ustalaj¹cy czêstotliwoœæ oscylatora k kondensator ustalaj¹cy czêstotliwoœæ oscylatora pF

57 BA9KV Schemat aplikacyjny Vcc 0k V V S 0p 0p 0p S 00 F fosc fosc F 00p

58 BA9KV BA9KV p F fosc 00p S V FB V O S SV k 00p k k 0p 0p A A A V O

59 BA9KV 9 BA9KV czterowyjœciowy sterownik zasilaczy impulsowych Schemat blokowy Vcc SCP Vref VOLTAGE REFERENCE S TIMER LATCH Q R BIAS DTC INV NON CAPH CAPL FB SCP OUT Vcc BIAS DTC INV CAPH CAPL FB OUT SCP P BIAS DTC INV CAPH CAPL FB SCP OUT Vcc BIAS DTC INV NON FB SCP CAPH CAPL OUT TRIANGLE FROM OSC OSC BUFFER ON/OFF LOGIC BA9KV R T C T STB STB STB STB STB

60 0 BA9KV Opis wyprowadzeñ uk³adu BA9KV Pin No. Pin name Function,, 9, CAPH,,, H connection for off transistor currentsetting capacitor,, 0, CAPL,,, L connection for off transistor currentsetting capacitor,,, OUT,,, Power transistor base connection, 9,, DTC,,, Dead time control, 0,, SCP,,, Output voltage monitor for Channels to protection, 0 NON, Noninverting input for error amplifier,,, 9 INV,,, Inverting input for error amplifier,,, FB,,, Error amplifier output,,, STB,,, Channel to Channel on / off switches RT Connection for resistor for triangularwave timing CT Connection for capacitor for triangularwave timing SCP Connection for capacitor for setting timing latch delay Ground 9 Vref Reference voltage output 0 Vcc Power supply input STB All Channel on / off switches,,, BIAS,,, Output current setting Vcc Power supply input for Channels and output stages P Ground connection for all output stages Vcc Power supply input for Channels and output stages Podstawowe parametry napiêcie zasilania. V czêstotliwoœæ oscylatora 0 00kHz pr¹d wyjœciowy 0mA

61 BA9F, BA9FS BA9F, BA9FS dwuwyjœciowy sterownik zasilaczy impulsowych Schemat blokowy Vref Vref NON INV FB NON INV FB Err Amp Err Amp Vcc CT RT 9 Reference Voltage SCP Comp Vref Triangle Oscillator PWM Comp PWM Comp OUT 0 OUT Vref Vref SCP S R R Timer UVLO Latch BA9F/FS DT DT Opis wyprowadzeñ uk³adów BA9F / BA9FS Pin No. Pin name Function CT External timing capacitor RT External timing resistor NON Positive input for error amplifier INV Negative input for error amplifier FB Error amplifier output DT Output dead time / soft start setting OUT Output Ground 9 Vcc Power supply 0 OUT Output DT Output dead time / soft start setting FB Error amplifier output INV Negative input for error amplifier NON Positive input for error amplifier SCP Time latch setting Vref Reference voltage output (.V) Podstawowe parametry napiêcie zasilania V CC. V pr¹d wyjœciowy I O 00mA moc rozproszenia P d 00mW dla BA9F 0mW dla BA9FS

62 BA9AFV BA9AFV dwuwyjœciowy sterownik zasilaczy impulsowych Schemat blokowy Vref Vref NON INV FB NON INV FB Err Amp Err Amp Vcc CT RT 9 Reference Voltage SCP Comp Vref Triangle Oscillator PWM Comp PWM Comp OUT 0 OUT Vref Vref SCP S R R Timer UVLO Latch BA9AFV DT DT Opis wyprowadzeñ uk³adu BA9AFV Podstawowe parametry Pin No. Pin name Function CT External timing capacitance RT External timing resistance NON Positive input for error amplifier INV Negative input for error amplifier FB Output for error amplifier DT Output dead time / soft start setting OUT Output Ground 9 Vcc Power supply 0 OUT Output DT Output dead time / soft start setting FB Output for error amplifier INV Negative input for error amplifier NON Positive input for error amplifier SCP Timer latch setting Vref Reference voltage (.0V) output napiêcie zasilania V CC. V pr¹d wyjœciowy I O 00mA czêstotliwoœæ oscylatora F OSC 0 00kHz napiêcie wyjœciowe V O V

63 BA9FV BA9FV dwuwyjœciowy sterownik zasilaczy impulsowych Vref NON INV FB NON INV FB SCP Err Amp Err Amp Schemat blokowy Vcc CT RT 9 Reference Voltage SCP Comp Vcc Triangle Oscillator PWM Comp PWM Comp Vref Vcc S R R Timer UVLO Latch DT DT BA9FV 0 OUT OUT

64 BA9FV Opis wyprowadzeñ uk³adu BA9FV Pin No. Pin name Function CT External timing capacitor RT External timing resistor NON Positive input for error amplifier INV Negative input for error amplifier FB Output for error amplifier DT Output dead time/soft start setting OUT Output Ground 9 Vcc Power supply 0 OUT Output DT Output dead time / soft start setting FB Output for error amplifier INV Negative input for error amplifier NON Positive input for error amplifier SCP Timer latch setting Vref Reference voltage output (.V) Podstawowe parametry napiêcie zasilania. V pr¹d wyjœciowy 0mA maksymalne napiêcie wyjœciowe V czêstotliwoœæ oscylatora 0 00kHz kondensator ustalaj¹cy czêstotliwoœæ oscylatora pF rezystor ustalaj¹cy czêstotliwoœæ oscylatora k

65 CS0 regulator napiêcia CS0 Schemat blokowy C OSC V CC V CC I C I C V REF.V.V V CC OK Oscillator Comparator A V CC.V CS0 G G V GATE FlipFlop R QN F S Q V FB 0.V Hold off Comp Comparator A.V RG V C V GATE PGnd V FB CS V REF =.V I T I T I T G.V.V.V CS Comparator A G A Slow Discharge Comparator Fault Comp.V R QN F G S Q Slow Discharge FlipFlop A CS Charge Sense Comparator.V Gnd Opis wyprowadzeñ uk³adu CS0 Nr wyprowadzenia Symbol Funkcja V GATE Sterowanie bramk¹ zewnêtrznego tranzystora PGnd Masa C OSC Kondensator ustalaj¹cy czêstotliwoœæ generatora Gnd Masa V FB Wejœcie napiêcia sprzê enia zwrotnego V CC Zasilanie czêœci logicznej CS Wyprowadzenie ³agodnego startu V C Zasilanie stopnia steruj¹cego

66 CS0 Schemat aplikacyjny VV C IN 0 MP IRF V GATE V GATE V C CS0 PGnd C OSC CS V CC RV CC 0 CS 0. D MBRS0 L.µH C OSC 0p Gnd V FB CV CC R B 0. V O.V@A R A.k C RR 0. C O 00 LeadSONarrow&PDIP V GATE PGnd CS0 V C CS C OSC V CC Gnd V FB

67 CS0 CS0 regulator napiêcia Schemat aplikacyjny V IN.V ±% R G D D MP R C D V GATE V C CS0 C C D PGnd C OSC CS V CC Short Circuit Timing Cap L C OSC CV CC Gnd V FB. reference R B V OUT R A C RR C O Lead SO Narrow & PDIP V GATE PGnd CS0 V C CS C OSC V CC Gnd V FB

68 CS CS regulator napiêcia V FB V FB SELEKT COMP I BIAS C OSC V REG C delay WDI 9 0 Schemat blokowy Multiplexer Switcher Error Amplifier COMP Logic Base Drive Current Sense Amplifier Oscillator CS Switcher Shutdown Over Voltage Linear Error Amplifier.V Current Limit Bandgap Reference Over Temperature RESET & Watchdog Timer.A,,,,,, 9 V IN V SW 0 Gnd ENABLE V LIN RESET