Wybrane firmowe programowalne cyfrowe układy scalone PLD

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1 Wybrane firmowe programowalne cyfrowe układy scalone PLD Układy Układy Układy Układy firmy Lattice firmy Altera firmy Xilinx innych firm Wykorzystano materiały firm: Altera, Actel, Cypress, Lattice, Xilinx 1

2 skróty,terminy (ogólne) ABEL ASIC ASSP ATE BST CPLD CLB DRAM DCI DCM DLL DSP EDA ESD FIFO FIR Fmax FPGA FSM Advanced Boolean Expression Language Application Specific Integrated Circuit Application Specific Standard Product Automatic Test Equipment Boundary Scan Test Complex Programmable Logic Device Configurable Logic Block Dynamic Random Access Memory Digitally Controlled Impedance Digital Clock Manager Delay-Locked Loop Digital Signal Processor Electronic Design Automation Electro-Static Discharge First In First Out Finite Impulse Response (Filter) Frequency Maximum Field Programmable Gate Array Finite State Machine 2

3 skróty,terminy (ogólne) GPS Geo-stationary Positioning System GUI Graphical User Interface IP Intellectual Property I/O Inputs and Outputs IRL Internet Reconfigurable Logic ISP In-System Programming JTAG Joint Test Advisory Group LSB Least Significant Bit LUT Look Up Table MPEG Motion Picture Experts Group MSB Most Significant Bit PCB Printed Circuit Board PCI Peripheral Component Interconnect PCMCIA Personal Computer Memory Card International Association PLA Programmable Logic Array PLD Programmable Logic Device PROM Programmable Read Only Memory EPROM Erasable Programmable Read Only Memory 3

4 skróty,terminy (ogólne) RAM Random Access Memory ROM Read Only Memory SPLD Simple Programmable Logic Device SRAM Static Random Access Memory Tpd Time of Propagation Delay through the device UMTS Universal Mobile Telecommunications System VHDL VHISC High Level Description Language VHSIC Very High Speed Integrated Circuit 4

5 Lattice - przegląd 5

6 Lattice - słowniczek skrótów ispgal OLMC GLB GRP MFB isplsi ispxpga ORCA ispgds ispgdx isppac - in system programmable Generic Array Logic Output Logic Macro Cell Generic Logic Block Global Routing Pool Multi-Function Block in system programmable Large Scale of Integration circuit in system programmable expanded field Programmable Gate Array Optimized Reconfigurable Cell Array in system progrrammable Generic Digital Switch array isp Generic Digital Crosspoint Device in system programmable Programmable Analog Circuit SERDES - SERializer - DESerializer 6

7 skróty,terminy (standardy I/O, wyprowadzenia,obudowy) HSTL LVCMOS LVTTL PCI SSTL Differential LDT LVDS RSDS Vcc0(V) High-Speed Transceiver Logic 1.5, 1.8 Low-Voltage CMOS 1.2, 1.5, 1.8, 2.5, 3.3 Low-Voltage Transistor-Transistor Logic 3.3 Peripheral Component Interconnect 3.0 Stub Series Terminated Logic 1.8, 2.5 Lightning Data Transport Low Voltage Differential Signaling Reduced-Swing Differential Signaling PLCC Plastic Leaded Chip Carrier TQFP Thin Quad Flat Pack PQFP Plastic Quad Flat Pack fpbga fine-pitch Ball Grid Array cabgachip array Ball Grid Array 7

8 Lattice - osiągnięcia 8

9 Lattice ispcpld 9

10 Lattice isplsi

11 Lattice isplsi

12 Lattice isplsi

13 Lattice isplsi

14 Lattice isplsi

15 Lattice ispxpld 5000MX 15

16 Lattice ispgdx 16

17 Lattice ispgdx - zastosowania 17

18 Szybka transmisja szeregowa 18

19 Analogowo/cyfrowy układ programowalny: isppac Power 19

20 Analogowe układy programowalne isppac

21 Przykład zastosowania w technice motoryzacyjnej 21

22 Zaawansowane obudowy i wyprowadzenia 22

23 Lattice - obudowy i wyprowadzenia 23

24 Altera - przegląd grup układów CPLD i FPGA 24

25 Altera - układy MAX 3000,..,

26 Altera - układy MAX 3000 tpd (ns) = Data path delay from input to non-registered output tsu (ns) = Global clock setup time tco1 (ns) = Delay from global clock to output fcnt (ns) = 16-bit counter internal global clock frequency 26

27 Altera - układy MAX właściwości High performance, low cost CMOS EEPROM based PLD's 3.3-V ISP through JTAG (Joint Test Action Group) the Built in boundary-scan test (BST) High density PLDs ranging from 600 to 10,000 gates 4.5 ns pin to pin logic delays counter frequencies of up to MHz MultiVolt I/O (core 3.3 V; I/O 5.0V,3.3V,2.5 V)levels Hot socketing support Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance 27

28 Altera - schemat blokowy układu MAX 3000A 28

29 Altera - makrokomórka logiczna układu MAX 3000A 29

30 Altera - układy FPGA typu FLEX10k, FLEX10kA Cechy szczególne: do typowych bramek Wbudowane bloki EAB (Embedded Array Blocks); w nich m.in. 2kb RAM Łatwość implementacji różnych funkcji logicznych Różne poziomy napięcia we/wy: 5.0V, 3.3V (FLEX10kA) FLEX 10kA toleruje 5V na wejściach Mały pobór mocy (prąd spoczynkowy <0.5 ma) FLEX 10KA zgodny ze standardem 3.3-V PCI Wbudowane układy do testowania krawędziowego (Boundary Scan Test) Rekonfigurowalne (ICR -In Circuit Reconfigurability) kilkoma metodami Szeroko konfigurowalne wejścia/wyjścia (m.in. Slew Rate dla zmniejszenia szumów - kosztem prędkości) Różne obudowy z liczbą wyprowadzeń od 84 do

31 Altera - układy FPGA typu FLEX10k 31

32 Altera - architektura układu FLEX10k 32

33 Altera - FLEX10k - wbudowany blok pamięci EAB 33

34 Altera - FLEX10k - blok logiczny LAB 34

35 Altera - FLEX10k - element logiczny LE 35

36 FLEX10k - tryby pracy LE : normalny, arytmetyczny 36

37 FLEX10k - licznikowe tryby pracy LE 37

38 Altera - FLEX10k - sumator z elementów LE 38

39 Altera - FLEX10k - koncepcja SameFrame 39

40 Xilinx - uklady CPLD Traditionally, CPLDs have used analog sense amplifiers to boost the performance of their architectures. This performance boost came at the cost of very high current requirements. CoolRunner-II RealDigital CPLDs, created by Xilinx, use an innovative all-digital core to achieve the same levels of performance at ultra-low power requirements. This allows designers to use the same CPLD architecture for both high-performance and low-power designs The removal of analog sense amplifiers also makes the architecture scaleable, allowing for aggressive cost reduction and feature enhancement with each successive process generation. 40

41 Xilinx - układy CPLD Why use a CPLD? CPLDs perform a variety of useful functions in systems design due to their unique capabilities. Reprogrammable - Change your design instantly for no cost as many times as you like, build reconfigurable systems, fix ASIC bugs, upgrade system functions anytime from anywhere; Saves time, lowers cost, simplifies design. Simple and easy to use - Designing with CPLDs is simple and easy, fits easily into existing design flow; Saves time, lowers cost, simplifies design. Low cost - Reprogram to fix system bugs, low unit cost, replace TTL and ASSPs to reduce board components and improve reliability; lowers design cost, lowers system cost, lowers maintenance cost. Nonvolatile - Programming kept on power down, CPLD functions available instantly on system power up, almost impossible to steal stored design; Improves security, simplifies design. Why use Xilinx CPLDs? As the market leader in programmable logic solutions, Xilinx provides a total solution to a designer's CPLD needs: Advanced Silicon - Cost-optimized chip design, high performance, low power operation, the widest range of packaging, advanced system features, highest I/O per macrocell counts. Free, powerful design tools - The ISE WebPACK design tools offer the most complete, easyto-use desktop software solution for developing any Xilinx CPLD. Everything else - Free reference designs and application notes, a design kit to get you started, a vast network of distributors, sales representatives, field application engineers, and inhouse technical support, and a wide array of online technical documentation. 41

42 Xilinx przegląd układów scalonych 42

43 Xilinx - FPGA - seria Virtex 43

44 Xilinx - rodzina FPGA: Spartan-3 44

45 Xilinx - Spartan-3 45

46 Xilinx - Spartan-3 : główne właściwości Revolutionary 90-nanometer process technology Very low cost, high-performance logic solution - Densities as high as 74,880 logic cells MHz system clock rate - Three separate power supplies for the core (1.2V), I/Os (1.2V to 3.3V), and special functions (2.5V) - Up to 784 I/O pins Mb/s data transfer rate per I/O - Seventeen single-ended signal standards - Six differential signal standards including LVDS - Termination by Digitally Controlled Impedance - Signal swing ranging from 1.14V to 3.45V - Double Data Rate (DDR) support Logic resources - Abundant, flexible logic cells with registers - Wide multiplexers - Fast look-ahead carry logic - Dedicated 18 x 18 multipliers - JTAG logic compatible with IEEE /1532 Standards - Up to 1,872 Kbits of total block RAM - Up to 520 Kbits of total distributed RAM Digital Clock Manager (up to four DCMs) - Clock skew elimination - Frequency synthesis - High resolution phase shifting 46

49 Xilinx - Spartan-3 The Spartan-3 family architecture consists of five fundamental programmable functional elements: Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical functions as well as to store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Twenty-three different signal standards, including six high-performance differential standards,. Double Data-Rate (DDR) registers are included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board designs. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. 49

50 Xilinx - Spartan-3 : architektura 50

51 Xilinx - Spartan-3 : I/O (1) 51

52 Xilinx - Spartan-3 : I/O (2) 52

53 Xilinx - Spartan-3 : I/O (2) The 53

54 Xilinx - Spartan-3 : "plasterki" w bloku CLB The 54

55 Xilinx - Spartan-3 : pamięć dwuwrotna RAM The 55

56 Xilinx - Spartan-3 : mnożarki 18x18 56

57 Xilinx - Spartan-3 : zarządzanie sygnałami zegarowymi The 57

58 Xilinx - Spartan-3 : rodzaje połączeń między blokami CLB The 58

59 Xilinx - Spartan-3 Configuration Spartan-3 FPGAs are programmed by loading configuration data into robust static memory cells that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master Serial, Slave Serial and Boundary Scan (JTAG). The Master and Slave Parallel modes use an 8-bit wide SelectMAP Port. The recommended memory for storing the configuration data is the low-cost Xilinx Platform Flash PROM family, which includes XCF00S PROMs for serial configuration and XCF00P PROMs for parallel configuration. 59

60 Xilinx - Spartan-3 : tryby programowania The Configuration Modes Spartan-3 supports the following five configuration modes: Slave Serial mode Master Serial mode Slave Parallel mode Master Parallel mode Boundary-Scan (JTAG) mode (IEEE 1532/IEEE ) 60