Temat 1 Wprowadzenie - cechy i rodziny procesorów sygnałowych

Temat 1 Wprowadzenie - cechy i rodziny procesorów sygnałowych 1

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Cechy procesorów sygnałowych https://en.wikipedia.org/wiki/digital_signal_processor Special arithmetic operations, such as fast multiply accumulates (MACs). Many fundamental DSP algorithms, such as FIR filters or the Fast Fourier transform (FFT) depend heavily on multiply accumulate performance. Hardware modulo addressing, allowing circular buffers to be implemented without having to constantly test for wrapping. A memory architecture designed for streaming data, using DMA extensively and expecting code to be written to know about cache hierarchies and the associated delays. Driving multiple arithmetic units may require memory architectures to support several accesses per instruction cycle Separate program and data memories (Harvard architecture), and sometimes concurrent access on multiple data busses Special SIMD (single instruction, multiple data) operations Some processors use VLIW techniques so each instruction drives multiple arithmetic units in parallel 10

Bit-reversed addressing, a special addressing mode useful for calculating FFTs Deliberate exclusion of a memory management unit. DSPs frequently use multi-tasking operating systems, but have no support for virtual memory or memory protection. Operating systems that use virtual memory require more time for context switching among processes, which increases latency. 11

Działanie procesora sygnałowego 12

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Procesory stałoprzecinkowe i zmiennoprzecinkowe 15

Rodziny procesorów Analog Devices 16

Zastosowania procesorów sygnałowych ADSP Portable and networked digital media appliances Consumer communications and networks Automotive telematics, safety driver assistant and infotainment Industrial, instrumentation, and medical Home theater audio systems Professional audio systems and Automotive audio systems Industrial and instrumentation equipment Medical imaging Telephony Wireless infrastructure WIMAX applications such as 802.16 and other advanced standards (e.g., OFDM) base-stations and software-defined radios Floating point, performance density related systems in both the single and multiprocessor environments Medical imaging equipment (e.g., CAT scan, Ultrasound, and MRI) Military equipment (e.g., radar/sonar, munitions targeting, and optoelectronics) Industrial and instrumentation equipment 17

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Blackfin 19

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Instrukcje multi-issue 32-bit ALU/MAC instruction 16-bit instruction 16-bit instruction Type of operations: Arithmetic Bit Logical Load immediate Move Shift or Rotate Vector (incl. Multiply-Accumulate) Video Pixel Type of operations: Load/Store Arithmetic (Ireg versions only) Type of operations: Load/Store (Ireg versions only) Przykład instrukcji: R3.H=(A1+=R0.L*R2.L), R3.L=(A0+=R0.H*R2.H) R2.H=W[I2++] R0=[I1--]; Mnożenie i dodawanie oraz załadowanie dwóch rejestrów. 22

Środowisko programistyczne 23

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Procesor TMS320C10 1982 r. Features Performance Up to 8.77 MIPs All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM 1.5K/4K/8K-Word On-Chip Program ROM 4K-Word On-Chip Program EPROM (TMS320E14/P14/E15/P15 25

Procesor TMS320C50 Features Powerful 16-Bit TMS320C5x CPU 20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation 25-, 40-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation Single-Cycle 16 16-Bit Multiply/Add 224K 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global) 2K, 4K, 8K, 16K, 32K 16-Bit Single-Access On-Chip Program ROM 1K, 3K, 6K, 9K 16-Bit Single-Access On-Chip Program/ Data RAM (SARAM) 1K Dual-Access On-Chip Program/ Data RAM (DARAM) Full-Duplex Synchronous Serial Port for Coder/Decoder Interface Time-Division-Multiplexed (TDM) Serial Port Hardware or Software Wait-State Generation Capability On-Chip Timer for Control Operations Repeat Instructions for Efficient Use of Program Space Buffered Serial Port Host Port Interface Multiple Phase-Locked Loop (PLL) Clocking Options ( 1, 2, 3, 4, 5, 9 Depending on Device) Block Moves for Data/Program Management 26

On-Chip Scan-Based Emulation Logic Boundary Scan Five Packaging Options o 100-Pin Quad Flat Package (PJ Suffix) o 100-Pin Thin Quad Flat Package (PZ Suffix) o 128-Pin Thin Quad Flat Package (PBK Suffix) o 132-Pin Quad Flat Package (PQ Suffix) o 144-Pin Thin Quad Flat Package (PGE Suffix) Low Power Dissipation and Power-Down Modes: o 47 ma (2.35 ma/ MIP) at 5 V, 40-MHz Clock (Average) o 23 ma (1.15 ma/ MIP) at 3 V, 40-MHz Clock (Average) o 10 ma at 5 V, 40-MHz Clock (IDLE1 Mode) o 3 ma at 5 V, 40-MHz Clock (IDLE2 Mode) o 5 ma at 5 V, Clocks Off (IDLE2 Mode) High-Performance Static CMOS Technology IEEE Standard 1149.1 Test-Access Port (JTAG) 27

Rodziny procesorów sygnałowych TI 28

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Karta DynaBit Część cyfrowa modułu TMS320C542 CPU Układ zegarowy Host PC Ukł. logiczne HPI Pamięć wewn. BSP Przetwornik A/C C/A CS4226 35

Programowanie Procesorów Sygnałowych TMS320C542 Features Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators 17-17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Data Bus With a Bus Holder Feature Address Bus With a Bus Holder Feature ( 548 and 549 Only) Extended Addressing Mode for 8M 16-Bit Maximum Addressable External Program Space ( 548 and 549 Only) 192K 16-Bit Maximum Addressable Memory Space (64K Words Program, 64K Words Data, and 64K Words I/O) On-Chip ROM with Some Configurable to Program/Data Memory Dual-Access On-Chip RAM Single-Access On-Chip RAM ( 548/ 549) Single-Instruction Repeat and Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better Program and Data Management Instructions With a 32-Bit Long Word Operand Instructions With Two- or Three-Operand Reads Arithmetic Instructions With Parallel Store and Parallel Load Conditional Store Instructions Fast Return From Interrupt On-Chip Peripherals o Software-Programmable Wait-State Generator and Programmable Bank Switching o On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source o Full-Duplex Serial Port to Support 8- or 16-Bit Transfers ( 541, LC545, and LC546 Only) o Time-Division Multiplexed (TDM) Serial Port ( 542, 543, 548, and 549 Only) o Buffered Serial Port (BSP) ( 542, 543, LC545, LC546, 548, and 549 Only) o 8-Bit Parallel Host-Port Interface (HPI) ( 542, LC545, 548, and 549) 36

o One 16-Bit Timer o External-Input/Output (XIO) Off Control to Disable the External Data Bus, Address Bus and Control Signals Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic 25-ns Single-Cycle Fixed-Point Instruction Execution Time [40 MIPS] for 5-V Power Supply ( C541 and C542 Only) 20-ns and 25-ns Single-Cycle Fixed-Point Instruction Execution Time (50 MIPS and 40 MIPS) for 3.3-V PowerSupply ( LC54x) 15-ns Single-Cycle Fixed-Point Instruction Execution Time (66 MIPS) for 3.3-V Power Supply ( LC54xA, 548, LC549) 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS) for 3.3-V Power Supply ( LC548, LC549) 10-ns and 8.3-ns Single-Cycle Fixed-Point Instruction Execution Time (100 and 120 MIPS) for 3.3-V Power Supply (2.5-V Core) ( VC549) 37

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Procesory dspic 39

Base-Line: 12-bit Instruction Word length, 8-bit Data Path Mid-Range: 14-bit Instruction Word length, 8-bit Data Path High-End: 16-bit Instruction Word length, 8-bit Data Path Enhanced: 16-bit Instruction Word length, 8-bit Data Path dspic30f/33f: 24-bit Instruction Word length, 16-bit Data Path 40

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Move Instructions Math Instructions Logic Instructions Rotate/Shift Instructions Bit Instructions Compare/Skip Instructions Program Flow Instructions Shadow/Stack Instructions Control Instructions DSP Instructions dspic30f/33f Instruction Groups 45

Instrukcje DSP w dspic 46

Ile cykli? 47

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Moduł dspicdem Adapter Zasilanie 9V Mikrokontroler dspic30f6014a Port RS-232 Potencjometr analogowy Port ICD 2 Piny I/O Low-pass filter Diody LED Low-pass filter dspicdem 80-Pin Starter Development Bard 49

Układ testowy ICD2+dsPICDEM 50

ARM ARM (Advanced RISC Machines) - firma projektująca mikroprocesory od lat 80 ubiegłego wieku zajmuje. Mikroprocesory są dziełem co najmniej dwóch firm ARM projektuje rdzeń, a producent układu (np. Atmel, ST, NXP) tworzy ostateczną konfigurację (ilość pamięci, układy peryferyjne) oraz produkuje fizyczny układ. http://www.arm.com/products/processors/cortex-m/index.php 51

http://forbot.pl/blog/artykuly/programowanie/kurs-stm32-2-podstawowe-informacje-ostm32-id4651 STM32xx, gdzie xx oznacza: F0 rdzeń Cortex-M0, tanie i proste układy, taktowane zegarem do 48MHz. F1 rdzeń Cortex-M3, zegar do 72MHz. Niektóre modele mają specjalne peryferia do sterowania silnikami. F2 mocniejsza wersja F1, zegar do 120MHz. F3 rdzeń Cortex-M4, zegar maksymalnie 72MHz, obsługa instrukcji DSP oraz arytmetyki liczb zmiennopozycyjnych. F4 mocniejsza wersja F3, taktowanie do 180MHz. F7 najnowsza wersja, przyspieszona względem F4, ponoć nawet dwa razy. L0 układ energooszczędny z rdzeniem Cortex-M0. L1 model energooszczędny z rdzeniem Cortex-M3. 52

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