RECONFIGURABLE UBIQUITOUS COMPUTING

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1 18 th Conference RECONFIGURABLE UBIQUITOUS COMPUTING RUC 2015 Szczecin, September, 2015

2 THURSDAY, 17 th September, :00 9:15 Conference Opening 9:15 10:30 SECTION: Wireless computing Chairman: Dariusz Frejlichowski 1. Stanisław Deniziak, Grzegorz Łukawski, Mariusz Bedla, Adam Krechowicz Scalable Distributed 2-layered Data Store (SD2DS) for Internet of Things (IoT) systems 2. Bartłomiej Gajewski, Tomasz Martyn Smart Mobile P2P communication optimization for close range by automatic interface switch 3. Jacek Borko, Grzegorz Dulnik, Adam Grzelka, Adam Łuczak, Adam Paszkowski Remote programming module of FPGA boards 4. Łukasz Łopaciński, Joerg Nolte, Steffen Buechner, Marcin Brzozowski, Rolf Kraemer 100 Gbps wireless - data link layer VHDL implementation 5. Łukasz Matuszewski, Wiktor Woźniak, Piotr Stołowski, Mieczysław Jessa A wireless data acquisition and processing system 10:30 11:00 Coffee Break 11:00 12:00 Presentations of Conference Partners 1. Grzegorz Samulnik National Instruments FPGA in rapid prototyping 2. Robert Ambrosewicz Tespol Data buses analysis based on mixed domain oscilloscope Tektronix MDO3000 series 12:00 13:15 SECTION: Methods and Tools 1 Chairman: Ryszard Szplet 1. Aleksandr Cariow, Galina Cariowa, Mira Witczak A FPGA-Oriented Fully Parallel Algorithm for multiplying dual quaternions 2. Leszek Ciopiński, Stanisław Deniziak Synthesis of Adaptive, Low Power Real Time Embedded Systems for ARM big.little Technology

3 3. Stanisław Deniziak, Tomasz Michno, Paweł Pięta Autonomous Monitoring System Based on Object Shape Detection 4. Przemysław Gąsior, Marta Gąsior Simulation and Implementation of Alternative Attitude Control Algorithms for Micro Multirotor Flying Platform 5. Grzegorz Grzęda, Ryszard Szplet Hardware/software development environment for SoC-based time interval counters 13:15 14:00 Lunch 14:00 15:15 SECTION: Methods and Tools 2 Chairman: Piotr Dziurzański 1. Piotr Kaczmarek, Tomasz Mańkowski, Jakub Tomczyński EOG event recognition method in EEG signal towards SSVEP BCI improvement 2. Paweł Kubczak, Łukasz Matuszewski, Mieczysław Jessa, Szymon Łoza Digital random bit generators implemented in FPGAs offered by various manufacturers 3. Mirosław Puczko Low Power BIST 4. Valery Salauyou FSM State Merging for Low Power 5. Krzysztof Sieczkowski, Tadeusz Sondej A method for testing the performance of a dual-core microcontroller with integrated program and data memory 16:00 17:00 Szczecin Philharmonic Sightseeing ul. Małopolska 48 18:00 21:00 Banquet (Cafe 22) PAZIM Building, pl. Rodła 8

4 FRIDAY, 18 th September, :00 10:30 SECTION: Hardware Issues Chairman: Aleksandr Cariow 1. Janusz Baczyński, Michał Baczyński Teleoperation system to remote control of robots 2. Zbigniew Jachna, Ryszard Szplet, Paweł Kwiatkowski, Krzysztof Różyc Parallel data processing in 3-channel integrated time-interval counter 3. Kamil Perko, Ryszard Szplet Programmable delay line 4. Krzysztof Różyc, Paweł Kwiatkowski, Marek Sawicki, Zbigniew Jachna, Ryszard Szplet Multichannel programmable distribution amplifier 5. Marek Sawicki, Krzysztof Różyc Time interval generator with STM32 microcontroller 6. Dominik Sondej, Ryszard Szplet A Study of the Effect of Temperature Changes on the Interpolating Time Counter 10:30 11:00 Coffee Break 11:00 12:30 SECTION: Hardware Acceleration Chairman: Valery Salauyou 1. Paweł Dąbal, Ryszard Pełka Pipelined architecture of the chaotic pseudo-random number generator in Cyclone V SoC device 2. Michał Fularz, Marek Kraft Hardware implementation of a decision tree classifier for object recognition applications 3. Michał Karwatowski, Kazimierz Wiatr The versatile hardware accelerator framework for sparse vector calculations 4. Szymon Łoza, Łukasz Matuszewski, Mieczysław Jessa, Paweł Kubczak A Random Number Generator Using Ring Oscillators and Keccak as Post-Processing 5. Marcin Pietroń, Marcin Wielgosz, Michał Karwatowski, Kazimierz Wiatr Study of the parallel techniques for dimensionality reduction and its impact on quality of the text processing algorithms

5 6. Marcin Pietroń, Michał Karwatowski, Kazimierz Wiatr The Java profiler based on byte code analysis and instrumentation for adaptation the source code in many-core hardware accelerators 12:30 13:00 Coffee Break 13:00 14:30 SECTION: Applications Chairman: Mirosław Łazoryszczak 1. Adam Bondyra, Stanisław Gardecki, Przemysław Gąsior Distributed control system for multirotor aerial platforms 2. Jacek Borko, Grzegorz Dulnik, Adam Grzelka, Adam Łuczak, Adam Paszkowski Parametric synthesizer of audio signals on FPGA 3. Grzegorz Dulnik, Adam Grzelka, Adam Łuczak Gigabit Ethernet interface with embedded lossless data encoder on FPGA 4. Sławomir Jaszczak, Piotr Nikończuk Temperature control algorithms for the refinishing spray booth 5. Sławomir Jaszczak, Piotr Nikończuk A model of the refinishing spray booth as a plant of automatic control 6. Tadeusz Sondej, Marek Sawicki, Ryszard Szplet Autonomous Microcontroller System for Controlling a Multi-channel Time Counter 15:00 Dinner Campanile Hotel ul. Wyszyńskiego 30