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1 Polska Akademia Nauk Oddział w Gdańsku Komisja Informatyki Metody Informatyki Stosowanej Nr 4/2008 (Tom 17) Szczecin 2008

2 Metody Informatyki Stosowanej Kwartalnik Komisji Informatyki Polskiej Akademii Nauk Oddział w Gdańsku Komitet Naukowy: Przewodniczący: prof. dr hab. inŝ. Henryk Krawczyk, czł. koresp. PAN, Politechnika Gdańska Członkowie: prof. dr hab. inŝ. Michał Białko, czł. rzecz. PAN, Politechnika Koszalińska prof. dr hab. inŝ. Ludosław Drelichowski, Uniwersytet Technologiczno-Przyrodniczy w Bydgoszczy prof. dr hab. inŝ. Janusz Kacprzyk, czł. koresp. PAN, Instytut Badań Systemowych PAN prof. dr hab. Jan Madey, Uniwersytet Warszawski prof. dr hab. inŝ. Leszek Rutkowski, czł. koresp. PAN, Politechnika Częstochowska prof. dr hab. inŝ. Piotr Sienkiewicz, Akademia Obrony Narodowej prof. dr inŝ. Jerzy Sołdek, Politechnika Szczecińska prof. dr hab. inŝ. Andrzej Straszak, Instytut Badań Systemowych PAN prof. dr hab. Maciej M. Sysło, Uniwersytet Wrocławski Recenzenci: prof. dr hab. inŝ. Ludosław Drelichowski, Uniwersytet Technologiczno-Przyrodniczy w Bydgoszczy dr hab. inŝ. Krzysztof Giaro, prof. PG, Politechnika Gdańska prof. dr hab. inŝ. Larysa Globa, National Technical University of Ukraine prof. dr hab. inŝ. Janusz Górski, Politechnika Gdańska prof. Shinya Kobayashi, Ehime University prof. dr hab. inŝ. Leonid Kompanets, Politechnika Częstochowska dr hab. inŝ. Georgy Kukharev, prof. PS, Politechnika Szczecińska dr hab. inŝ. Eugeniusz Kuriata, prof. UZ, Uniwersytet Zielonogórski dr hab. inŝ. Emma Kusztina, prof. PS, Politechnika Szczecińska dr hab. inŝ. Karol Myszkowski, Politechnika Szczecińska prof. dr hab. inŝ. Andrzej Piegat, Politechnika Szczecińska dr hab. Jacek Pomykała, Uniwersytet Warszawski prof. dr hab. inŝ. Remigiusz Rak, Politechnika Warszawska prof. dr hab. inŝ. Valeriy Rogoza, Politechnika Szczecińska dr hab. inŝ. Khalid Saeed, prof. PB, Politechnika Białostocka prof. dr hab. inŝ. Boris Sovetov, St. Petersburg Electrotechnical University dr hab. inŝ. Antoni Wiliński, prof. PS, Politechnika Szczecińska dr hab. Zenon Zwierzewicz, prof. AM, Akademia Morska w Szczecinie Redaktor Naczelny: Antoni Wiliński Sekretarz redakcji: Piotr Czapiewski ISSN ISBN Wydawnictwo: Polska Akademia Nauk Oddział w Gdańsku Komisja Informatyki Adres kontaktowy: ul. śołnierska 49 p. 104, Szczecin Druk: Pracownia Poligraficzna Wydziału Informatyki Politechniki Szczecińskiej Nakład 510 egz.

3 Spis treści Włodzimierz Bielecki, Krzysztof Kraska INCREASING DATA LOCALITY OF PARALLEL PROGRAMS EXECUTED IN EMBEDDED SYSTEMS Bartosz Bielski, Przemysław Klęsk PASSIVE OPERATING SYSTEM FINGERPRINTING USING NEURAL NETWORKS AND INDUCTION OF DECISION RULES Janusz Bobulski ANALYSIS OF 2D PROBLEM IN HMM Michał Choraś, Adam Flizikowski, Anna Stachowicz, Marta Redo, Rafał Renk, Witold Hołubowicz ONTOLOGY NOTATION AND DESCRIPTION OF VULNERABILITIES IN HETEROGENEOUS NETWORKS AND CRITICAL INFRASTRUCTURES Magdalena Ciszczyk, Emma Kusztina THE ROLE OF STANDARDIZATION IN THE PROCESS OF FORMING QUALITY OF EDUCATIONAL REPOSITORY IN ODL Paweł Forczmański UNIFIED JPEG AND JPEG-2000 COLOR DESCRIPTOR FOR CONTENT-BASED IMAGE RETRIEVAL.. 53 Dariusz Frejlichowski AN OUTLINE OF THE SYSTEM FOR COMPUTER-ASSISTED DIAGNOSIS BASED ON BINARY ERYTHROCYTES SHAPES Jarosław Jankowski PERSONALIZACJA PRZEKAZU INTERAKTYWNEGO Z UDZIAŁEM METOD ANALIZY CZYNNIKOWEJ.. 71 Henryk Krawczyk, Sławomir Nasiadka METODA WYZNACZANIA KONTEKSTU DLA APLIKACJI STEROWANYCH ZDARZENIAMI Mariusz Kubanek, Szymon Rydzek A HYBRID METHOD OF PERSON VERIFICATION WITH USE INDEPENDENT SPEECH AND FACIAL ASYMMETRY Krzysztof Makles IDENTYFIKACJA CHARAKTERYSTYK MODELI W TRYBIE ON-LINE WRAZ Z WIZUALNĄ REKONSTRUKCJĄ CHARAKTERYSTYKI Wojciech Maleika, Michał Pałczyński VIRTUAL MULTIBEAM ECHOSOUNDER IN INVESTIGATIONS ON SEA BOTTOM MODELING Radosław Mantiuk HDRLIB: BIBLIOTEKA DO SZYBKIEGO PRZETWARZANIA OBRAZÓW HDR WYKORZYSTUJĄCA ZAAWANSOWANE MOśLIWOŚCI PROCESORÓW CPU Ireneusz Mrozek, Eugenia Buslowska, Bartosz Sokol MPS(3N) TRANSPARENT MEMORY TEST FOR PATTERN SENSITIVE FAULT DETECTION Adam Nowosielski, Krzysztof Kłosowski ANALIZA NATĘśENIA RUCHU OSÓB NA MONITOROWANYCH OBSZARACH

4 4 Walenty Oniszczuk MODELLING AND ANALYSIS OF TWO-SERVER NETWORKS WITH FINITE CAPACITY BUFFERS AND BLOCKING Jerzy Pejaś DIRECTED THRESHOLD SIGNCRYPTION SCHEME FROM BILINEAR PAIRING UNDER SOLE CONTROL OF DESIGNATED SIGNCRYPTER Andrzej Piegat, Marek Landowski LACK OF INFORMATION AVERAGE DISTRIBUTION OF PROBABILITY DENSITY Jacek Pomykała, Bartosz Źrałek DYNAMIC GROUP THRESHOLD SIGNATURE BASED ON DERANDOMIZED WEIL PAIRING COMPUTATION Orest Popov, Anna Barcz, Piotr Piela DETERMINING THE EFFECTIVE TIME INTERVALS IN THE RECURRENT PROCESSES OF IDENTIFICATION OF DYNAMIC SYSTEMS Michał Słonina, Imed El Fray INFRASTRUKTURA ZARZĄDZANIA UPRAWNIENIAMI WYKORZYSTUJĄCA KONTROLĘ DOSTĘPU OPARTĄ NA ROLACH ZINTEGROWANĄ Z JĄDREM SYSTEMU OPERACYJNEGO Marcin Suchorzewski EVOLVING WEIGHTED TOPOLOGIES FOR NEURAL NETWORKS USING GENETIC PROGRAMMING Galina łariova, Alexandr łariov EFEKTYWNE ALGORYTMY WYZNACZANIA WYRAśENIA POSTACI Y=(A B)X Tatiana Tretyakova, Abdullah Zair FORMATION OF THE CONTENTS OF KNOWLEDGE'S BASES FOR LOCAL INTELLIGENT DECISION SUPPORT SYSTEMS Jarosław Wątróbski, Zbigniew Piotrowski IMPACT OF THE PRESENCE OF LINGUISTIC DATA ON THE DECISION AID PROCESS

5 Increasing data locality of parallel programs executed in embedded systems Włodzimierz Bielecki, Krzysztof Kraska Szczecin University of Technology, Faculty of Computer Science and Information Technology Abstract: Increasing data locality in a program is a necessary factor to improve performance of software parts of embedded systems, to decrease power consumption and reduce memory on chip size. A possibility of applying a method of quantifying data locality to a novel method of extracting synchronization-free threads is introduced. It can be used to agglomerate extracted synchronization-free threads for adopting a parallel program to a target architecture of an embedded system under various loop schedule options (spacetime mapping) and the influence of well-known techniques to improve data locality. The choice of the best combination of loop transformation techniques regarding to data locality makes possible improving program performance. A way of an analysis of data locality is presented. Experimental results are depicted and discussed. Conclusion and future research are outlined. Keywords: data locality, compilers, parallel processing, embedded systems 1. Introduction Embedded systems involved in data processing consist of programmable processors, program components processed by the processors and hardware components often realized in FPGA cooperating with software parts of the system. Software components enable making corrections quickly, code reusing, elastic changing a program permitting for reducing the time of delivering product to the market. But programmable processors consume considerably more energy and they are significantly slower than their hardware counterparts. Hardware solutions assure greater performance and smaller power consumption however designing time may be long and the design process is expensive [9]. Multiprocessor architectures for embedded systems are widespread on the contemporary electronic market. For example, the Xilinx FPGA Virtex-4FX chip includes up to two PowerPC405 processors, National Semiconductor s Geode chips enable to join several processors to build a multiprocessor system based on the x86 architecture, the HPOC project (Hundred Processors, One Chip) undertaken at Hewlett Packard attempts to consolidate hundreds of processors on one chip using co-resident on-chip memory [4].

6 6 Włodzimierz Bielecki, Krzysztof Kraska Similarly to the computer software development, the embedded system development needs programming languages, debuggers, compilers, linkers and other programming tools. Approved as an IEEE standard, the SystemC language is an example of the tool that enables the implementation of both software and hardware parts of embedded systems. The optimal implementation of software components designed for multiprocessor embedded systems is critical for their performance and the power consumption. However, poor data locality is a common feature of many existing numerical applications [6]. Such applications are often represented with affine loops where the considerable quantities of data placed in arrays exceeded the size of a fast but small cache memory. For an inefficient code, referenced data has to be fetched to a cache from external memory although they could be reused many times. Because cache is expensive, memories often operate at full speed of a processor while cheaper but more capacious external memory modules operate at several times slower frequency, hence the time to access data located in a cache memory is significantly less. Improvement in data locality can be obtained by means of high-level program transformations. Increasing data locality within a program improves the utilization of fast data cache and delimits accesses to slower memory modules at lower level. Finally it makes general performance improvement for software parts of embedded systems. 2. Analysis of data locality for synchronization-free slices A new method of extracting synchronization-free slices (SFS) in arbitrarily nested loops was introduced in [1]. The method enables us to extract more parallel threads than other methods. The well-known technique invented by Wolfe [3] estimates data reuse factors. It makes possible to adopt such order of the loop execution that increases data locality in a program. In relation to the method of extracting synchronization-free slices, the estimation of data locality is a necessary activity to obtain an improved performance for a program executed on a target architecture. The SFS method extracts maximal number of the parallel threads however any target embedded architecture consists of the fixed number of CPU cores usually smaller than the number of threads extracted. Hence, it is necessary to adjust the level of parallelism in a program to the target architecture [10]. Our previous research conducted on parallel computers indicates that the extraction of synchronization-free slices as well as applying the tiling and the array contraction techniques within an individual thread can considerably increase the performance of a parallel program. For example, the results of the experiments performed for the Livermore Loops Kernel 1 (hydro fragment) [5] and the matrix multiplication algorithm [6] indicate the considerable gains in the execution time (Figure 1a and Figure 1b) [2]. On the contrary, the example of a simple code in Figure 2 executed on the same target architecture proves that the extraction of parallel slices under certain circumstances can limit the performance of a program the execution time of the parallel code (8 seconds) was about 30% greater than that of the correspondent sequential code (6 seconds). It can be noticed that the parallel code has the decreased spatial-reuse factor value for a reference to the array a[] caused to maintain the coherence between the caches of multiple processors to a large extent.

7 Increasing data locality of parallel programs executed in embedded systems 7 (a) Figure 1. Execution time of (a) Livermore Loops Kernel 1 (b) matrix multiplication (b) #define SIZE int main(void) { double *a = new double[size]; for(long i=0; i<size; i++) a[i]=(double)i+1; for(long i=0; i<(size-2); i++) a[i+2]=sin((a[i]*size+1)/size); return 0; } (a) Sequential code #include <omp.h> #define SIZE int main(void) { omp_set_num_threads(2); double *a=new double[size]; for(long i=0; i<size; i++) a[i]=(double)i+1; #pragma omp parallel for private(j,i) shared(a) for(long j=0; j < 2 ; j++) for(long i=j; i<(size-2); i+=2) a[i+2]=sin((a[i]*size+1)/size); return 0; } (b) Parallel code Figure 2. Decreased performance in the parallel version of a simple code

8 8 Włodzimierz Bielecki, Krzysztof Kraska The assurance of the optimal performance for a program with the level of parallelism limited to the possibility of a target architecture requires the iterative estimation of data locality for different ways of the slices agglomeration in combination with different types of scheduling (space-time mapping) and applying well-known techniques for improving data locality. The choice of the best combination of the above-mentioned elements under a generalized data locality factor will assure the optimal performance of a program. For both of the Livermore Loops Kernel 1 and the matrix multiplication algorithm, the level of parallelism was adjusted to a target architecture by applying the function omp_set_num_threads( omp_get_num_procs( ) ) from the OpenMP library. The number of threads created for the target architecture (2 x Intel Pentium 4 with Hyper-Threading technology) was 4. The size of the DataCache-L1 line for the processor was 128-bytes which corresponds to 32 array elements. Since the directive #pragma parallel in the both programs omitted the type of the iteration scheduling, the compiler applied the scheduling of the static policy allocating ¼ consecutive iterations to each thread [12]. The data locality factors for the matrix multiplication algorithm and the Livermore Loops Kernel 1 calculated with the method [3] are presented in Table 1, Table 2 and Table 3. Table 1. Reuse factors for the matrix multiplication algorithm Reuse factors Reference Temporal Spatial Self-reuse k j i k j i R k R j R i R k * Cumulative self reuse R j * R i * F k * Data footprint z[i][j] N N 32 1 N 32N 32N 1 N/32 N 2 /128 x[i][k] 1 N N N 32N N/32 N/32 N 2 /128 y[k][j] 1 1 N/ N/ N N N 2 /32 N 2 /32 F j * F i * Σ N + 33 N + 64 N/4 + 2 N+33 64N N N+N/ N 2 /32 + N/16 6N 2 /128 In the case of the matrix multiplication, there are no separate references to the same array, therefore only the self-reuse factors were calculated. For arrays of size N x N, where N=2048, the data footprint for the outermost loop, Fi*, considerably exceeded the size of DataCache-L1 causing an access to slower memory level: F 2 N * = ; N = 2048 ; F i = * 6 i

9 Increasing data locality of parallel programs executed in embedded systems 9 Table 2. Temporal-reuse factors for the Livermore Loops Kernel 1 (hydro fragment) Reuse factors Reference Temporal Spatial Self-reuse Cumulative self reuse Data footprint k l k l R k R l * R k * R l * F k * F l x[k] 1 Loop loop 32 32loop n/32 n/128 y[k] 1 Loop loop 32 32loop n/32 n/128 Z[k+10] 1 Loop loop 32 32loop n/32 n/128 Z[k+11] 1 Loop loop 32 32loop n/32 n/128 Σ 128 4* loop * loop n/8 n/32 Table 3. Spatial-reuse factors for the Livermore Loops Kernel 1 (hydro fragment) Reuse factors Reference Self-spatial reuse Group-temporal reuse Cumulative group reuse k l k l k l z[k+11] z[k+10] loop 32 32*loop The value Fi*= for the 4-bytes array element size gives 768KB. After applying the tiling technique and splitting data into blocks with the side B=32 elements, the value of the data footprint was decreased because that data amount could be entirely placed in DataCache-L1: F 2 B = ; B = 32 ; 128 * 6 i F = 48. The value Fi*=48 for the 4-bytes array element size gives 192B. It should be noticed that DataCache-L1 was shared between 2 parallel threads. In the case of the Livermore Loops Kernel 1 (hydro fragment), the self-reuse factors are identical for the source with fine grained parallelism and the source with synchronization-free slices extracted. There is also the group-reuse between references z[k+11] and z[k+10] sorted so that the reuse distance between adjacent references is lexicographically nonnegative. There are also self-temporal and self-spatial reuse factors for the both references. The group-spatial reuse factor equals one since there is the self-spatial reuse factor. To take into account reuse between references, a generalized data reuse factor for the outermost loop Ll is computed by dividing the data footprint by the cumulative group reuse factor that finally gives: * i n / 32 2 n / (32 * loop) 32* loop =. 3. Experiments Experiments were performed by means of the software simulator IBM PowerPC Multi-Core Instruction Set Simulator v1.29 (MC-ISS) [7] intended for the PowerPC

10 10 Włodzimierz Bielecki, Krzysztof Kraska 405/440/460 embedded systems development and the related IBM RISCWatch v6.0i debugger [8]. Cache utilization was reached from DCU (sim readdcu) statistics of the simulator. The following configuration of the simulator was used to conduct experiments: 2 x PowerPC405 processors with 16KB two-way set-associative DataCache-L1 (8 words/32 bytes cache line) no DataCache-L2. The sources exposed to the experiments were developed in a manner representative for the embedded software development using the cross-platform development environment composed of the Intel PC workstation and the target executable architecture [8]. The examined C sources were compiled on the Fedora 4 Linux x86 to the PowerPC Embedded ABI file format by means of the gcc compiler and executed in the target system environment using the MC-ISS software simulator. Due to the target architecture limitations, two threads of the data processing were extracted in the sources. Iterations of a parallel loop were assigned to threads according to the scheduling of static policy, i.e., one thread has assigned a half of the consecutive loop iterations [12]. Table 4 shows the results achieved for the matrix multiplication code being simulated in the MC-ISS embedded software simulator. Table 4. The experimental results of DCU utilization for the matrix multiplication code (N=256, B=8) RISCWatch STATUS Parallel SFS with Parallel SFS Sequential Parallel SFS Blocking & with Blocking Array Contraction CPU0 CPU1 CPU0 CPU1 CPU0 CPU1 CPU0 CPU1 DCU total accesses N/A DCU misses N/A Misses/total [%] 6,8% N/A 6,8% 6,8% 0,22% 0,22% 0,27% 0,27% Table 5 shows the results obtained for the Livermore loop Kernel 1 (hydro fragment) code executed in the MC-ISS embedded software simulator. RISCWatch STATUS Table 5. The experimental results of DCU utilization for the Kernel 1 (loop=100; array_size=8192*sizeof(int)) Parallel SFS with Sequential Parallel Parallel SFS Array Contraction CPU0 CPU1 CPU0 CPU1 CPU0 CPU1 CPU0 CPU1 DCU total accesses N/A DCU misses N/A misses/total [%] 2,69% N/A 2,69% 2,69% 0,04% 0,04% 0,06% 0,06% The examined sources have achieved the same (in the first case) and much better (in the second case) DCU misses/total ratio after synchronization-free slices extraction.

11 Increasing data locality of parallel programs executed in embedded systems 11 Obviously, increase in performance of the programs by the parallel execution with no synchronizations is not considered in the tables. Applying the blocking technique has further improved data locality. For the Parallel SFS sources with the array contraction technique applied the misses/total ratio do not properly render data locality improveplaced in CPU registers and therefore DCU total accesses ment since reused data were factors were decreased. In fact, data locality is better then previously due to usage of the fastest memory registers. The results achieved in the foregoing experiments confirmed the results previously achieved for real multiprocessor computers. They indicated on the significant improvea PowerPC405 processor used in embedded systems ment of the DCU utilization for where well-known optimization techniques to improved data locality were applied within synchronization-free slices. 4. A source-to-source compiler We intend to implement the results of our research in an academic source-to-source compiler. Figure 3 illustrates the structural overview of the software to be build. Figure 3. A structural overview of the software to build based on the results of research The MainController is responsible for managing the execution of all compiler modules. The SlicesExtractionModule implements the method of extracting parallel synchronization-free slices [1]. It makes the extraction of slices from an input C source taking advantage of the Omega Calculator Library [11] to fulfill a dependence analysis. The LoopTransformationModule analyses possible combinations of the slices agglome- scheduling options as well as techniques for improving data locality (i.e. tiling and array contraction). The DataLocalityEstimationModule implements the method of calculating data locality factors. VOPC domain model of the module worked out during research is presented in Fig- ration and applies into output code various space-timure 4. Both latter modules use the linear algebra engine from the Wolfram Research s

12 12 Włodzimierz Bielecki, Krzysztof Kraska Mathematica package. The CodeGenerationModule is responsible for the generation of source code destined for the target architecture; there is the explicit assumption that the tool will be able to generate output code according to the OpenMP2.0 standard. 5. Conclusion Figure 4. VOPC Domain Model of the DataLocalityEstimationModule The estimation of data locality for parallel threads of a loop extracted by means of the method introduced in [1] is a necessary activity to assure optimal performance for a program adjusted to and executed in a targeted architecture. The experiments presented in this paper targeted to an embedded system environment indicate on the identical gains achieved through the increased utilization level of DCU for sources where wellknown optimization techniques to improved data locality were applied. An important observation obtained from the research is that other software components of the system simultaneously worked during the program execution have an unforeseen impact on the cache utilization. For this reason, it is correctly to assume that the available cache size is different for various configurations of the system. To optimize cache utilization, it is worth to estimate the actual size of available cache memory. Let be noticed that the limitations of using the results of our work go from the limitations of the method introduced in [3]. It applies group-reuses only to separate array references that indexes expressions produce the same coefficient matrix A. Our effort is targeted toward the expansion of the presented method to operate the cases where: A i + c = A i + c

13 Increasing data locality of parallel programs executed in embedded systems 13 References [1] Bielecki W., Siedlecki K. Extracting synchronization-free slices in perfectly nested uniform and non-uniform loops. Electonic Modeling, [2] Bielecki W., Kraska K., Siedlecki K. Increasing Program Locality by Extracting Synchronization-Free Slices in Arbitrarily Nested Loops. Proceedings of the Fourteenth International Multi-Conference on Advanced Computer Systems ACS2007, [3] Wolfe M. High Performance Compilers for Parallel Computing. Addison-Wesley, [4] Richardson S. MPOC. A Chip Multiprocessor for Embedded Systems. [online] HP Laboratories, [5] Netlib Repository at UTK and ORNL [online]. [6] Aho A. V., Lam M. S., Sethi R., Ullman J. D. Compilers: Principles, Techniques and Tools, 2nd Edition. Addison-Wesley, [7] IBM PowerPC Multi-Core Instruction Set Simulator. User s Guide, IBM Corporation, [8] IBM RISCWatch Debugger. User s Manual, IBM Corporation, [9] Stasiak A. Klasyfikacja Systemów Wspomagających Proces Przetwarzania i Sterowania. II Konferencja Naukowa KNWS'05, [10] Griebl M. Habilitation. Automatic Parallelization of Loop Programs for Distributed Memory Architectures. Iniversitat Passau, [11] Kelly W., Maslov V., Pugh W., Rosser E., Shpeisman T., Wonnacott D. The omega library interface guide. Technical Report CS-TR-3445, University of Maryland, [12] Chandra R., Dagum L., Kohr D., Maydan D., McDonald J., Menon R. Parallel Programing In OpenMP. Morgan Kaufmann, 2001.

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15 Passive operating system fingerprinting using neural networks and induction of decision rules Bartosz Bielski, Przemysław Klęsk Szczecin University of Technology, Faculty of Computer Science and Information Technology Abstract: One of the most difficult task for people managing big- or even medium-size computer network is determining the accurate number of hosts that are protected. This information is really helpful for accurately configuring network-based devices such as intrusion detection systems. Exact knowledge of the operating systems (residing in hosts) can be useful for excluding many alerts that cannot apply to a remote operating system that is being examined. In this context, we consider a classification problem (we try to recognize the class of operating system) when some of the characteristics of the system are modified by its user or any other program (e.g. for internet connection tuning). We use neural networks (MLP, RBF) and rule induction techniques. It should be stressed that existing fingerprinting tools get high accuracy results when tested on the clean versions of operating systems, but they fail to detect systems with modified TCP/IP parameters. Keywords: passive OS fingerprinting, TCP/IP fingerprinting, operating systems recognition, neural networks, induction of decision rules 1. Introduction Accurate operating system fingerprinting by passive analysis of the network traffic can be used for maintaining a security access policy. This type of policy may list the types of hosts that are allowed and disallowed (for example administrator can disallow really old versions of operating systems which may have serious bugs). Remote operating systems fingerprinting is the way of determining the operating system of a remote host. It is based on the fact that the the TCP/IP protocol specification does not clearly describe how to use all fields in the TCP and IP header. Due to this fact developers of operating systems implement differently the TCP/IP stack which can be used for identification. Even versions and patches can be identified, because programmers are using e.g. other security features in the systems. Remote operating systems can be identified by three approaches just looking, active and passive fingerprinting. Just looking method is really not accurate and may give inadequate results, because of the easy way to modify given presented information; active scanning provides detailed information by actively sending packets and passive analysis provides real-time (but usually less detailed) information. Nevertheless, scanning consumes hosts resources and network bandwidth and it requires more time on

16 16 Bartosz Bielski, Przemysław Klęsk broad networks. Moreover, it can cause some network devices to stop servicing. Passive fingerprinting hase none of the flaws mentioned above. Figure 1. OSI and TCP/IP stack (source: Passive fingerprinting is a method of recognizing operating systems based only on the packet traffic which is already transmitted. There is no need to send extra packets to remote host, because all the packets may be used to identify attacker or any person that is doing a security audit. A main goal of this research is to determine how accurately remote operating systems can be detected using passive fingerprinting by means of neural networks and induction of decision rules. Other goal is to evaluate the fingerprinting on some usermodified TCP/IP stacks on which current recognition tools fail to work and determine how well neural networks can identify operating systems that were not in the training set. 2. Passive OS fingerprinting existing solutions Based on our observations, which were confirmed by some of earlier researches [3], we can say that currently existing fingerprinting tools are mostly: rule based (very simple rules) or nearest neighbour implementation (usually 1-NN). Using such approach there is no way to accurately fingerprint operating systems having any modifications that were not included in the fingerprinting database of the systems. On the other hand, there is no way to include all such information in the database because of the variety of possible modifications.

17 Passive operating system fingerprinting using neural networks Passive OS fingerprinting using neural networks We try the application of neural networks MLP, RBF to our problem, knowing their successful application in such pattern-recognition areas as: handwriting recognition, identifying vehicles, medicine, etc. The database of the operating systems was taken from the open-source tool named ettercap [13], which at present includes the largest set of the OS examples The structure of values included in the ettercap set of operating systems is presented in Figure 2. WWWW : 4 digit hex field indicating the TCP Window Size MSS : 4 digit hex field indicating the TCP Option Maximum Segment Size if omitted in the packet or unknown it is "_MSS" TTL : 2 digit hex field indicating the IP Time To Live WS : 2 digit hex field indicating the TCP Option Window Scale if omitted in the packet or unknown it is "WS" S : 1 digit field indicating if the TCP Option SACK permitted is true N : 1 digit field indicating if the TCP Options contain a NOP D : 1 digit field indicating if the IP Don't Fragment flag is set T : 1 digit field indicating if the TCP Timestamp is present F : 1 digit ascii field indicating the flag of the packet S = SYN A = SYN + ACK LEN : 2 digit hex field indicating the length of the packet if irrelevant or unknown it is "LT" OS : an ascii string representing the OS Figure 2. TCP/IP parameters used to identify operating system (source: ettercap database) First of all, different detailed versions of operating systems were grouped into larger classes in order to have a sensible proportion: number of examples / number of classes, see Table 1. Experiments in which we tried to identify the exact OS version were conducted later. As seen on Figure 3 in state of full knowledge about operating systems and full trust researched neural network can identify systems with about 100% probability, just like current rule-based tools. There is already very rare situation when we can give trust computers and systems we do not own.

18 18 Bartosz Bielski, Przemysław Klęsk Table 1. Operating systems classes Pos. OS class Number of examples 1. windows linux bsd other solaris unix mac_os network modem/router cisco device network printer 39 Figure 3. Results of recognition by many kinds of neural networks When the knowledge and trust drops and especially when we cannot trust remote systems are clean and unmodified, neural network get really good prediction results. The good scores are especially valuable when there is no strict signature in the database of operating systems so that system cannot be recognised at all. As seen on Figure 4 we compared best neural network from earlier researches (3- layer multi layer perceptron network MLP with 10 neurons in every hidden layer) with multi-stage neural network architecture that can detect operating system version

19 Passive operating system fingerprinting using neural networks 19 too. The multi-stage architecture was build only for systems that meet the minimum 1% occurrence of quantity (Windows, Linux, BSD, etc). Figure 4. Results by recognition depth Figure 5. Best neural network topology (3 layers, 10 neurons in every hidden layer) One should note that: for modified TCP/IP stacks and when the original signatures were not placed in the training set the network gives 97,7% correct classification rate. When trying to additionally determine the exact version of the OS the rate dropped, but still was very high 85%. 4. Induction of decision rules, Pareto-optimal optimal rules To have a better understanding of the data set we also decided to do the induction of decision rules. Discovering interesting and statistically relevant rules may allow to perform simple OS fingerprinting without a neural network classifier, since if-then rules are of high interpretive value for humans.

20 20 Bartosz Bielski, Przemysław Klęsk 4.1. Greedy induction of decision rules Say we want to find all possible rules with the length of premise equal to p, i.e. in the premise there are exactly p terms connected with and. For example, when p = 3 a possible rule is: if ( x = 2) and ( x = 3) and ( x = 1) then ( y = 2) p=3 The algorithm to find all such rules can be named as greedy meaning that we will ( ) iterate over all n p combinations of input variables x j and for each single combination we will also iterate over all possible settings of values for these variables. The exact total number of iterations in such an algorithm (and in the same time the total number of rules) can be calculated as follows. Let n, p ( ) C be the set of all n p combinations of indices of variables. E.g.: C = {(1,2),(1,3),(1,4),(2,3),(2,4),(3,4)}. The 4,2 exact number of iterations is then equal to m m m j, j,, j p C n p ( 1 2 ), j 1 j 2 j p And if we wanted to find all rules with premises of length equal to p or less than p then the number of iterations (and rules) is. (1) p m m m k j, j,, j k C n k =1 ( 1 2 ), j 1 j 2 j k. (2) For a single fixed premise what should be the value chosen as the decision? Let X be a general notation for the premise and Y for the decision, e.g.: if ( x = 2) and ( x = 3) and ( x = 1) then ( y = 2) X = x Y = y Then, for a fixed premise X = x we deal with a certain conditional probability distribution of decisions P( Y X = x ). In other words, from the whole data set we take the subset containing only the cases where X = x and within this subset we look at the distribution of different decisions y {1, 2,, m y }. As the decision value we choose such y for which P( Y = y X = x ) is maximal Rule assessment measures Each rule should be assigned a certain number assessing how interesting this rule is and how statistically relevant it is for the decision. The most basic and common meas-

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